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PIC16F785 Data Sheet
20-Pin Flash-Based 8-Bit CMOS Microcontroller with Two-Phase Asychronous Feedback PWM, Dual High-Speed Comparators and Dual Operational Amplifiers
2004 Microchip Technology Inc.
Preliminary
DS41249A
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Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41249A-page ii
Preliminary
2004 Microchip Technology Inc.
PIC16F785
20-Pin Flash-Based 8-Bit CMOS Microcontroller
High-Performance RISC CPU
* Only 35 instructions to learn: - All single-cycle instructions except branches * Operating speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle * Interrupt capability * 8-level deep hardware stack * Direct, Indirect and Relative Addressing modes
Peripheral Features
* High-speed Comparator module with: - Two independent analog comparators - Programmable on-chip voltage reference (CVREF) module (% of VDD) - 1.2V band gap reference - Comparator inputs and outputs externally accessible - < 40 ns propagation delay - 2 mv offset, typical * Operational amplifier module with 2 independent op amps: - 3 MHz GBWP, typical - All I/O pins externally accessible * Two-Phase Asychronous Feedback PWM module: - Complementary output with programmable overlap/dead band delay - Infinite resolution analog duty cycle - Sync Output/Input for multi-phase PWM - FOSC/2 maximum PWM frequency * A/D Converter: - 10-bit resolution and 14 channels (2 internal) * 17 I/O pins and 1 input-only pin: - High-current source/sink for direct LED drive - Interrupt-on-pin change - Individually programmable weak pull-ups * Timer0: 8-bit timer/counter with 8-bit programmable prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator, if INTOSC mode selected * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Capture, Compare, PWM module: - 16-bit Capture, max resolution 12.5 ns - Compare, max resolution 200 ns - 10-bit PWM with 1 output channel, max frequency 20 kHz * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
Special Microcontroller Features
* Precision Internal Oscillator: - Factory calibrated to 1% - Software selectable frequency range of 8 MHz to 32 kHz - Software tunable - Two-Speed Start-up mode - Crystal fail detect for critical applications - Clock mode switching during operation for power savings * Power-saving Sleep mode * Wide operating voltage range (2.0V-5.5V) * Industrial and Extended temperature range * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Reset (BOR) with software control option * Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable * Multiplexed Master Clear with pull-up/input pin * Programmable code protection * High-Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years
Low-Power Features
* Standby Current: - 30 nA @ 2.0V, typical * Operating Current: - 8.5 A @ 32 kHz, 2.0V, typical - 100 A @ 1 MHz, 2.0V, typical * Watchdog Timer Current: - 1 A @ 2.0V, typical * Timer1 Oscillator Current: - 2 A @ 32 kHz, 2.0V, typical
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 1
PIC16F785
Program Memory Device Flash (words) PIC16F785 2048 SRAM (bytes) 128 EEPROM (bytes) 256 17+1 Data Memory I/O 10-bit A/D (ch) Operational Amplifiers Comparators CCP 2 Phase PWM Timers 8/16-bit
12
2
2
1
1
2/1
Pin Diagram
20-pin PDIP, SOIC, SSOP
VDD RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5/CCP1 RC4/C2OUT/PH2 RC3/AN7/C12IN3-/OP1 RC6/AN8/OP1RC7/AN9/OP1+ RB7/SYNC
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VSS RA0/AN0/C1IN+/ICSPDAT RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 RB4/AN10/OP2RB5/AN11/OP2+ RB6
DS41249A-page 2
Preliminary
PIC16F785
2004 Microchip Technology Inc.
PIC16F785
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 9 3.0 Clock Sources ............................................................................................................................................................................ 23 4.0 I/O Ports ..................................................................................................................................................................................... 33 5.0 Timer0 Module ........................................................................................................................................................................... 47 6.0 Timer1 Module with Gate Control............................................................................................................................................... 49 7.0 Timer2 Module ........................................................................................................................................................................... 53 8.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 55 9.0 Comparator Module.................................................................................................................................................................... 61 10.0 Voltage References.................................................................................................................................................................... 69 11.0 Operational Amplifier (OPA) Module .......................................................................................................................................... 73 12.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 77 13.0 Two-Phase PWM ....................................................................................................................................................................... 87 14.0 Data EEPROM Memory ............................................................................................................................................................. 99 15.0 Special Features of the CPU.................................................................................................................................................... 103 16.0 Instruction Set Summary .......................................................................................................................................................... 123 17.0 Development Support............................................................................................................................................................... 133 18.0 Electrical Specifications............................................................................................................................................................ 139 19.0 Packaging Information.............................................................................................................................................................. 161 Appendix A: Data Sheet Revision History.......................................................................................................................................... 165 Appendix B: Migrating from other PICmicro(R) DeviceS...................................................................................................................... 165 Index .................................................................................................................................................................................................. 167 On-Line Support................................................................................................................................................................................. 173 Systems Information and Upgrade Hot Line ...................................................................................................................................... 173 Reader Response .............................................................................................................................................................................. 174 Product Identification System ............................................................................................................................................................ 175
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Errata
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2004 Microchip Technology Inc.
Preliminary
DS41249A-page 3
PIC16F785
NOTES:
DS41249A-page 4
Preliminary
2004 Microchip Technology Inc.
PIC16F785
1.0 DEVICE OVERVIEW
This document contains device specific information for the PIC16F785. Additional information may be found in the PICmicro(R) Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this Data Sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F785 is covered by this Data Sheet. It is available in 20-pin PDIP, SOIC and SSOP packages. Figure 1-1 shows a block diagram of the PIC16F785 device. Table 1-1 shows the pinout description.
FIGURE 1-1:
PIC16F785 BLOCK DIAGRAM
INT CONFIGURATION 13 PROGRAM COUNTER FLASH 2k X 14 PROGRAM MEMORY DATA BUS 8 PORTA RA0 RA1 8-LEVEL STACK (13-BIT) RAM 128 BYTES FILE REGISTERS RAM ADDR 9 PORTB RB4 INDIRECT ADDR RB5 RB6 RB7 FSR REG PORTC Status REG 8 RC0 RC1 3 POWER-UP TIMER INSTRUCTION DECODE & CONTROL OSCILLATOR START-UP TIMER POWER-ON RESET WATCHDOG TIMER BROWN-OUT DETECT INTERNAL OSCILLATOR BLOCK 8 W REG RC2 MUX RC3 RC4 RC5 ALU RC6 RC7 RA2 RA3 RA4 RA5
PROGRAM BUS
14
INSTRUCTION REG DIRECT ADDR 7
ADDR MUX
8
OSC1/CLKIN OSC2/CLKOUT
TIMING GENERATION
OP1 OP1+ Dual Op Amps OP1OP2 OP2+ OP2EEDATA 256 BYTES DATA EEPROM EEADDR 8
CCP1 MCLR VDD VSS
T1G T1CKI TIMER0 T0CKI TIMER1
TIMER2
CCP
2 Phase PWM
PH1 PH2 SYNC
ANALOG-TO-DIGITAL CONVERTER
Voltage Reference
2 ANALOG COMPARATORS
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN3 AN8 AN9 AN10 AN11
VREF
C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
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Preliminary
DS41249A-page 5
PIC16F785
TABLE 1-1: PIC16F785 PINOUT DESCRIPTION
Pin Function
19 RA0 AN0 C1IN+ ICSPDAT RA1 AN1 C12IN0VREF ICSPCLK RA2 AN2 T0CKI INT C1OUT RA3 MCLR VPP RA4 AN3 T1G OSC2 CLKOUT RA5 T1CKI OSC1 CLKIN RB4 AN10 OP2RB5 AN11 OP2+ RB6 RB7 SYNC RC0 AN4 C2IN+ RC1 AN5 C12IN1PH1 RC2 AN6 C12IN2OP2 RC3 AN7 C12IN3OP1
Name
RA0/AN0/C1IN+/ICSPDAT
Input Type
TTL AN AN ST TTL AN AN AN ST ST AN ST ST -- TTL ST HV TTL AN ST -- -- TTL ST XTAL ST TTL AN -- TTL AN -- TTL TTL ST TTL AN AN TTL AN AN -- TTL AN AN -- TTL AN AN --
Output Type
CMOS -- -- CMOS CMOS -- -- AN -- CMOS -- -- -- CMOS -- -- -- CMOS -- -- XTAL CMOS CMOS -- -- -- CMOS -- AN CMOS -- AN OD CMOS CMOS CMOS -- -- CMOS -- -- CMOS CMOS -- -- AN CMOS -- -- AN
Description
PORTA I/O w/ prog. pull-up and interrupt-on-change A/D Channel 0 input Comparator 1 non-inverting input Serial Programming Data I/O PORTA I/O w/ prog. pull-up and interrupt-on-change A/D Channel 1 input Comparator 1and 2 inverting input External Voltage Reference for A/D, buffered reference output Serial Programming Clock PORTA I/O w/ prog. pull-up and interrupt-on-change A/D Channel 2 input Timer0 clock input External Interrupt Comparator 1 output PORTA input w/ prog. pull-up and interrupt-on-change Master Clear w/ internal pull-up Programming voltage PORTA I/O w/ prog. pull-up and interrupt-on-change A/D Channel 3 input Timer1 gate Crystal/Resonator FOSC/4 output PORTA I/O w/ prog. pull-up and interrupt-on-change Timer1 clock Crystal/Resonator External clock input/RC oscillator connection PORTB I/O A/D Channel 10 input Op Amp 2 inverting input PORTB I/O A/D Channel 11 input Op Amp 2 non-inverting input PORTB I/O. Open drain output PORTB I/O Master PWM sync output or slave PWM sync input PORTC I/O A/D Channel 4 input Comparator 2 non-inverting input PORTC I/O A/D Channel 5 input Comparator 1 and 2 inverting input PWM phase 1 output PORTC I/O A/D Channel 6 input Comparator 1 and 2 inverting input Op Amp 2 output PORTC I/O A/D Channel 7 input Comparator 1 and 2 inverting input Op Amp 1 output
RA1/AN1/C12IN0-/VREF/ICSPCLK
18
RA2/AN2/T0CKI/INT/C1OUT
17
RA3/MCLR/VPP
4
RA4/AN3/T1G/OSC2/CLKOUT
3
RA5/T1CKI/OSC1/CLKIN
2
RB4/AN10/OP2-
13
RB5/AN11/OP2+
12
RB6 RB7/SYNC RC0/AN4/C2IN+
11 10 16
RC1/AN5/C12IN1-/PH1
15
RC2/AN6/C12IN2-/OP2
14
RC3/AN7/C12IN3-/OP1
7
DS41249A-page 6
Preliminary
2004 Microchip Technology Inc.
PIC16F785
TABLE 1-1: PIC16F785 PINOUT DESCRIPTION (CONTINUED)
Pin Function
6
Name
RC4/C2OUT/PH2
Input Type
Output Type
Description
RC4 TTL CMOS PORTC I/O C2OUT -- CMOS Comparator 2 output PH2 -- CMOS PWM phase 2 output RC5/CCP1 5 RC5 TTL CMOS PORTC I/O CCP1 ST CMOS Capture input/Compare output RC6/AN8/OP18 RC6 TTL CMOS PORTC I/O AN8 AN -- A/D Channel 8 input OP1AN -- Op Amp 1 inverting input RC7/AN9/OP1+ 9 RC7 CMOS PORTC I/O AN9 AN -- A/D Channel 9 input OP1+ AN -- Op Amp 1 non-inverting input VSS 20 VSS Power -- Ground reference VDD 1 VDD Power -- Positive supply Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, AN = Analog, OD = Open Drain output, HV = High Voltage
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 7
PIC16F785
NOTES:
DS41249A-page 8
Preliminary
2004 Microchip Technology Inc.
PIC16F785
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
2.2
Data Memory Organization
The PIC16F785 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. Only the first 2k x 14 (0000h-07FFh) for the PIC16F785 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 2k x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F785
PC<12:0>
The data memory (see Figure 2-2) is partitioned into four banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h - 7Fh in Bank 0 and A0h - BFh in Bank 1 are General Purpose Registers, implemented as static RAM. The last sixteen register locations in Bank 1 (F0h - FFh), Bank 2 (170h - 17Fh), and Bank 3 (1F0h - 1FFh) point to addresses 70h - 7Fh in Bank 0. All other RAM is unimplemented and returns `0' when read. Seven address bits are required to access any location in a data memory bank. Two additional bits are required to access the four banks. When data memory is accessed directly, the seven least significant address bits are contained within the opcode and the two most significant bits are contained in the Status register. RP0 and RP1 (Status<5> and Status<6>) are the two most significant data memory address bits and are also known as the bank select bits. Table 2-1 lists how to access the four banks of registers.
CALL, RETURN RETFIE, RETLW
13
STACK LEVEL 1 STACK LEVEL 2
STACK LEVEL 8 RESET VECTOR
TABLE 2-1:
000H
BANK SELECTION
RP1 RP0 0 1 0 1 0 0 1 1
Bank0
INTERRUPT VECTOR 0004 0005 ON-CHIP PROGRAM MEMORY 07FFH 0800H
Bank1 Bank2 Bank3
2.2.1
GENERAL PURPOSE REGISTER FILE
1FFFH
The register file banks are organized as 128 x 8 in the PIC16F785. Each register is accessed, either directly, by seven address bits within the opcode, or indirectly, through the File Select Register, FSR. When the FSR is used to access data memory, the eight least significant data memory address bits are contained in the FSR and the ninth most significant address bit is contained in the IRP bit (Status<7>) of the Status register. (See Section 2.4 "Indirect Addressing, INDF and FSR Registers").
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-2). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 9
PIC16F785
FIGURE 2-2: DATA MEMORY MAP OF THE PIC16F785
File Address Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(1) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(1) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON
PCLATH INTCON PIE1 PCON OSCCON OSCTUNE ANSEL0 PR2 ANSEL1 WPUA IOCA REFCON VRCON EEDATA EEADR EECON1 EECON2(1) ADRESL ADCON1 General Purpose Register 32 Bytes
PCLATH INTCON
PCLATH INTCON
PWMCON1 PWMCON0 PWMCLK PWMPH1 PWMPH2
WDTCON
CM1CON0 CM2CON0 CM2CON1 OPA1CON OPA2CON
ADRESH ADCON0
General Purpose Register 96 Bytes 6Fh 70h 7Fh
BFh C0h EFh F0h FFh 16Fh 170h 17Fh 1EFh 1F0h 1FFh
accesses Bank 0 Bank1
accesses Bank 0 Bank2
accesses Bank 0 Bank3
Bank 0
Unimplemented data memory locations, read as `0'.
Note 1: Not a physical register.
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Preliminary
2004 Microchip Technology Inc.
PIC16F785
TABLE 2-2:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF TMR0 PCL STATUS FSR PORTA(1) PORTB(1) PORTC(1) -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON -- -- WDTCON -- -- -- -- -- ADRESH ADCON0 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's register Program Counter's (PC) Least Significant Byte IRP -- RB7 RC7 Unimplemented Unimplemented -- GIE EEIF Unimplemented Holding register for the Least Significant Byte of the 16-bit TMR1 Holding register for the Most Significant Byte of the 16-bit TMR1 T1GINV -- TMR1GE TOUTPS3 T1CKPS1 TOUTPS2 T1CKPS0 TOUTPS1 T1OSCEN TOUTPS0 T1SYNC TMR2ON TMR1CS T2CKPS1 TMR1ON T2CKPS0 -- PEIE ADIF -- T0IE CCP1IF Write buffer for upper 5 bits of program counter INTE C2IF RAIE C1IF T0IF OSFIF INTF TMR2IF RAIF TMR1IF RP1 -- RB6 RC6 RP0 RA5 RB5 RC5 TO RA4 RB4 RC4 PD RA3 -- RC3 Z RA2 -- RC2 DC RA1 -- RC1 C RA0 -- RC0 Indirect data memory address pointer xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --x0 x000 xx00 ---00xx 0000 -- -- ---0 0000 0000 0000 0000 0000 -- xxxx xxxx xxxx xxxx 0000 0000 0000 0000 -000 0000 xxxx xxxx xxxx xxxx CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 -- -- -- -- WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 -- -- -- -- -- xxxx xxxx ADON 0000 0000 22,110 47,110 21,110 15,110 22,110 33,110 40,110 43,110 -- -- 21,110 17,110 19,110 -- 49,110 49,110 51,110 53,110 53,110 55,110 55,110 55,110 -- -- 118,110 -- -- -- -- -- 79,110 81,110 Name
PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Page
Timer2 Module register
Capture/Compare/PWM Register1 Low Byte Capture/Compare/PWM Register1 High Byte -- Unimplemented Unimplemented -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Most Significant 8 bits of the left justified A/D result or 2 bits of right justified result ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE -- DC1B1 DC1B0
Legend: Note 1:
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition. shaded = unimplemented Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read `0' immediately after a reset even though the data latches are either undefined (POR) or unchanged (other resets).
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DS41249A-page 11
PIC16F785
TABLE 2-3:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh INDF Addressing this location uses contents of FSR to address data memory (not a physical register) INTEDG T0CS T0SE PSA PS2 PS1 PS0 OPTION_REG RAPU PCL STATUS FSR TRISA TRISB TRISC -- -- PCLATH INTCON PIE1 -- PCON OSCCON OSCTUNE ANSEL0 PR2 ANSEL1 -- WPUA IOCA -- REFCON VRCON EEDAT EEADR EECON1 EECON2 ADRESL ADCON1 Program Counter's (PC) Least Significant Byte IRP -- TRISB7 TRISC7 RP1 -- TRISB6 TRISC6 RP0 TRISA5 TRISB5 TRISC5 TO TRISA4 TRISB4 TRISC4 PD TRISA3 -- TRISC3 Z TRISA2 -- TRISC2 DC TRISA1 -- TRISC1 C TRISA0 -- TRISC0 Indirect data memory address pointer xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx --11 1111 1111 ---1111 1111 -- -- -- PEIE ADIE -- IRCF2 -- ANS6 -- -- T0IE CCP1IE -- IRCF1 -- ANS5 -- WPUA5 IOCA5 BGST VRR EEDAT5 EEADR5 Write buffer for upper 5 bits of program counter INTE C2IE SBOREN IRCF0 TUN4 ANS4 -- WPUA4 IOCA4 VRBB -- EEDAT4 EEADR4 RAIE C1IE -- OSTS(1) TUN3 ANS3 ANS11 WPUA3(2) IOCA3 VREN VR3 EEDAT3 EEADR3 T0IF OSFIE -- HTS TUN2 ANS2 ANS10 WPUA2 IOCA2 VROE VR2 EEDAT2 EEADR2 WREN INTF TMR2IE POR LTS TUN1 ANS1 ANS9 WPUA1 IOCA1 CVROE VR1 EEDAT1 EEADR1 WR RAIF TMR1IE BOR SCS TUN0 ANS0 ANS8 WPUA0 IOCA0 -- VR0 EEDAT0 EEADR0 RD ---0 0000 0000 0000 0000 0000 -- ---1 --qq -110 q000 ---0 0000 1111 1111 1111 1111 ---- 1111 -- --11 1111 --00 0000 -- --00 000000- 0000 0000 0000 0000 0000 ---- x000 ---- ---xxxx xxxx -- -000 ---22,110 16,110 21,110 15,110 22,110 34,110 40,110 43,110 -- -- 21,110 17,110 18,110 -- 20,110 32,110 27,110 80,110 53,110 80,111 -- 34,111 35,111 -- 71,111 70,111 99,111 99,111 100,111 100,111 78,111 81,111 Name
PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Page
Unimplemented Unimplemented -- GIE EEIE -- -- -- ANS7 --
Unimplemented
Timer2 Module Period register Unimplemented -- -- -- -- Unimplemented -- C1VREN EEDAT7 EEADR7 -- C2VREN EEDAT6 EEADR6
-- -- -- -- WRERR EEPROM Control register 2 (not a physical register) -- ADCS2 ADCS1 ADCS0 --
Least Significant 2 bits of the left justified result or 8 bits of the right justified result -- --
Legend: Note 1: 2:
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented OSTS bit OSCCON <3> reset to `0' with Dual Speed Start-up and LP, HS, or XT selected as the oscillator. RA3 pull-up is enabled when MCLRE is `1' in Configuration Word.
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TABLE 2-4:
Addr Bank 2 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note 1: INDF TMR0 PCL STATUS FSR PORTA(1) PORTB(1) PORTC(1) -- -- PCLATH INTCON -- -- -- -- PWMCON1 PWMCON0 PWMCLK PWMPH1 PWMPH2 -- -- -- -- CM1CON0 CM2CON0 CM2CON1 OPA1CON OPA2CON -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's register Program Counter's (PC) Least Significant Byte IRP -- RB7 RC7 Unimplemented Unimplemented -- GIE Unimplemented Unimplemented Unimplemented Unimplemented OVRLP PRSEN PWMASE POL POL COMOD1 PASEN PWMP1 C2EN C2EN COMOD0 BLANK2 PWMP0 C1EN C1EN CMDLY4 BLANK1 PER4 PH4 PH4 CMDLY3 SYNC1 PER3 PH3 PH3 CMDLY2 SYNC0 PER2 PH2 PH2 CMDLY1 PH2EN PER1 PH1 PH1 CMDLY0 PH1EN PER0 PH0 PH0 -- PEIE -- T0IE Write buffer for upper 5 bits of program counter INTE RAIE T0IF INTF RAIF RP1 -- RB6 RC6 RP0 RA5 RB5 RC5 TO RA4 RB4 RC4 PD RA3 -- RC3 Z RA2 -- RC2 DC RA1 -- RC1 C RA0 -- RC0 Indirect data memory address pointer xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --x0 x000 xx00 ---00xx 0000 -- -- ---0 0000 0000 0000 -- -- -- -- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- C1OE C2OE -- -- -- C1POL C2POL -- -- -- C1SP C2SP -- -- -- C1R C2R -- -- -- C1CH1 C2CH1 T1GSS -- -- C1CH0 C2CH0 C2SYNC -- -- 0000 0000 0000 0000 00-- --10 0--- ---0--- ----- -- 22,110 47,110 21,110 15,110 22,110 33,110 40,110 43,110 -- -- 21,110 17,110 -- -- -- -- 95,111 89,111 90,111 91,111 92,111 -- -- -- -- 63,111 65,111 66,111 74,111 74,111 -- -- Name
PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Page
Unimplemented Unimplemented Unimplemented Unimplemented C1ON C2ON MC1OUT OPAON OPAON Unimplemented Unimplemented C1OUT C2OUT MC2OUT -- --
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read `0' immediately after a reset even though the data latches are either undefined (POR) or unchanged (other resets).
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Preliminary
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PIC16F785
TABLE 2-5:
Addr Bank 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: INDF Addressing this location uses contents of FSR to address data memory (not a physical register) INTEDG T0CS T0SE PSA PS2 PS1 PS0 OPTION_REG RAPU PCL STATUS FSR TRISA TRISB TRISC -- -- PCLATH INTCON PIE1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Program Counter's (PC) Least Significant Byte IRP -- TRISB7 TRISC7 RP1 -- TRISB6 TRISC6 RP0 TRISA5 TRISB5 TRISC5 TO TRISA4 TRISB4 TRISC4 PD TRISA3 -- TRISC3 Z TRISA2 -- TRISC2 DC TRISA1 -- TRISC1 C TRISA0 -- TRISC0 Indirect data memory address pointer xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx --11 1111 1111 ---1111 1111 -- -- -- PEIE ADIE -- T0IE CCP1IE Write buffer for upper 5 bits of program counter INTE C2IE RAIE C1IE T0IF OSFIE INTF TMR2IE RAIF TMR1IE ---0 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 22,110 16,110 21,110 15,110 22,110 34,110 40,110 43,110 -- -- 21,110 17,110 18,110 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Name
PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Page
Unimplemented Unimplemented -- GIE EEIE
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
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2.2.2.1 Status Register
The Status register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the Reset status * the bank select bits for data memory (SRAM) The Status register can be the destination for any instruction, like any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the Status register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Status register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the "Instruction Set Summary". Note: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS -- STATUS REGISTER (ADDRESS: 03h OR 83h)
R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7
IRP: Register bank select bit (used for indirect addressing) 1 = Bank 2,3 (100h - 1FFh) 0 = Bank 0,1 (00h - FFh) RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) For borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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Preliminary
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PIC16F785
2.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to `1' (OPTION_REG<3>). See Section 5.4 "Prescaler". The OPTION register is a readable and writable register, which contains various control bits to configure: * * * * TMR0/WDT prescaler External RA2/INT interrupt TMR0 Weak pull-ups on PORTA
REGISTER 2-2:
OPTION_REG -- OPTION REGISTER (ADDRESS: 81h)
R/W-1 RAPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual port latch values in WPUA register INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/AN2/T0CKI/INT/C1OUT pin 0 = Interrupt on falling edge of RA2/AN2/T0CKI/INT/C1OUT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA2/AN2/T0CKI/INT/C1OUT pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/AN2/T0CKI/INT/C1OUT pin 0 = Increment on low-to-high transition on RA2/AN2/T0CKI/INT/C1OUT pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 Note 1: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TMR0 Rate WDT Rate(1) 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
A dedicated 16-bit WDT postscaler is available for the PIC16F785. See Section 15.6 "Watchdog Timer (WDT)" for more information.
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2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts.
REGISTER 2-3:
INTCON -- INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RAIE R/W-0 T0IF R/W-0 INTF R/W-0 RAIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RA2/AN2/T0CKI/INT/C1OUT External Interrupt Enable bit 1 = Enables the RA2/AN2/T0CKI/INT/C1OUT external interrupt 0 = Disables the RA2/AN2/T0CKI/INT/C1OUT external interrupt RAIE: PORTA Change Interrupt Enable bit(1) 1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt T0IF: TMR0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RA2/AN2/T0CKI/INT/C1OUT External Interrupt Flag bit 1 = The RA2/AN2/T0CKI/INT/C1OUT external interrupt occurred (must be cleared in software) 0 = The RA2/AN2/T0CKI/INT/C1OUT external interrupt did not occur RAIF: PORTA Change Interrupt Flag bit 1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software) 0 = None of the PORTA <5:0> pins have changed state Note 1: 2: IOCA register must also be enabled. T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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Preliminary
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PIC16F785
2.2.2.4 PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 2-4.
REGISTER 2-4:
PIE1 -- PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0 EEIE bit 7 R/W-0 ADIE R/W-0 CCP1IE R/W-0 C2IE R/W-0 C1IE R/W-0 OSFIE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt C2IE: Comparator 2 Interrupt Enable bit 1 = Enables the Comparator 2 interrupt 0 = Disables the Comparator 2 interrupt C1IE: Comparator 1 Interrupt Enable bit 1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt TMR2IE: Timer 2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer 2 to PR2 match interrupt 0 = Disables the Timer 2 to PR2 match interrupt TMR1IE: Timer 1 Overflow Interrupt Enable bit 1 = Enables the Timer 1 overflow interrupt 0 = Disables the Timer 1 overflow interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC16F785
2.2.2.5 PIR1 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.
REGISTER 2-5:
PIR1 -- PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
R/W-0 EEIF bit 7 R/W-0 ADIF R/W-0 CCP1IF R/W-0 C2IF R/W-0 C1IF R/W-0 OSFIF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started ADIF: A/D Interrupt Flag bit 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode C2IF: Comparator 2 Interrupt Flag bit 1 = Comparator 2 output has changed (must be cleared in software) 0 = Comparator 2 output has not changed C1IF: Comparator 1 Interrupt Flag bit 1 = Comparator 1 output has changed (must be cleared in software) 0 = Comparator 1 output has not changed OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating TMR2IF: Timer 2 to PR2 Match Interrupt Flag bit 1 = Timer 2 to PR2 match occurred (must be cleared in software) 0 = Timer 2 to PR2 match has not occurred TMR1IF: Timer 1 Overflow Interrupt Flag bit 1 = Timer 1 register overflowed (must be cleared in software) 0 = Timer 1 has not overflowed Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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Preliminary
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PIC16F785
2.2.2.6 PCON Register
The Power Control (PCON) register (See Table 15-2) contains flag bits to differentiate between a: * * * * Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
The PCON register bits are shown in Register 2-6.
REGISTER 2-6:
PCON -- POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0 -- bit 7 U-0 -- U-0 -- R/W-1 SBOREN U-0 -- U-0 -- R/W-0 POR R/W-x BOR bit 0
bit 7-5 bit 4
Unimplemented: Read as `0' SBOREN: Software BOR Enable bit(1) 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Resetoccurred (must be set in software after a Brown-out Reset occurs) Note 1: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown BOREN<1:0> = 01 in Configuration Word for this bit to control the BOR.
bit 3-2 bit 1
bit 0
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PIC16F785
2.3 PCL and PCLATH
FIGURE 2-3:
PCH 12 PC 5 PCLATH<4:0> 8 ALU RESULT 8 7
The Program Counter (PC) specifies the address of the instruction to fetch for execution. The program counter is 13 bits wide. The low byte is called the PCL register. The PCL register readable and writable. The high byte of the PC (PC<12:8>) is called the PCH register. This register contains PC<12:8> bits which are not directly readable or writable. All updates to the PCH register go through the PCLATH register. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH).
LOADING OF PC IN DIFFERENT SITUATIONS
PCL INSTRUCTION WITH 0 PCL AS DESTINATION
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 OPCODE <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
2.3.1
MODIFYING PCL 2.3.3 STACK
Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by first writing the desired upper 5 bits to the PCLATH register. When the lower 8 bits are then written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions, or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. For more information refer to Application Note DS00556, "Implementing a Table Read".
The PIC16F785 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth PUSH overwrites the value that was stored from the first PUSH. The tenth PUSH overwrites the second PUSH (and so on). Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called push or pop. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.
2.3.2
PROGRAM MEMORY PAGING
The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper bit of the address is provided by PCLATH<3> (page select bit). When doing a CALL or GOTO instruction the user must ensure that the page select bit is programmed so that the desired destination program memory page is addressed. When the CALL instruction (or interrupt) is executed, the entire 13-bit PC return address is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the RETURN or RETFIE instructions which pop the address from the stack.
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Preliminary
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PIC16F785
2.4 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM location 20h - 2Fh using indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit (Status<7>), as shown in Figure 2-4.
EXAMPLE 2-1:
MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE
INDIRECT ADDRESSING
;initialize pointer ;to RAM ;clear INDF register ;increment pointer ;all done? ;no clear next ;yes continue
0x20 FSR INDF FSR FSR,4 NEXT
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING PIC16F785
INDIRECT ADDRESSING 0 IRP 7 FILE SELECT REGISTER 0
DIRECT ADDRESSING RP1 RP0 6 FROM OPCODE
BANK SELECT
LOCATION SELECT 00 00H 01 10 11
BANK SELECT 180H
LOCATION SELECT
DATA MEMORY
7FH BANK 0 BANK 1 BANK 2 BANK 3
1FFH
For memory map detail see Figure 2-2.
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3.0
3.1
CLOCK SOURCES
Overview
The PIC16F785 can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. EC - External clock with I/O on RA4. LP - 32.768 kHz watch crystal or ceramic resonator oscillator mode. XT - Medium gain crystal or ceramic resonator oscillator mode. HS - High gain crystal or ceramic resonator mode. RC - External Resistor-Capacitor (RC) with FOSC/4 output on RA4 RCIO - External Resistor-Capacitor with I/O on RA4. INTOSC - Internal Oscillator with FOSC/4 output on RA4 and I/O on RA5. INTOSCIO - Internal Oscillator with I/O on RA4 and RA5.
The PIC16F785 has a wide variety of clock sources and selection features to allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the PIC16F785 clock sources. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and resistor-capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal via software. * Two-speed Clock Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch to the internal oscillator.
Clock source modes are configured by the FOSC<2:0> bits in the Configuration Word (See Section 15.0 "Special Features of the CPU"). Once the PIC16F785 is programmed and the clock source mode configured, it cannot be changed in software.
FIGURE 3-1:
PIC16F785 CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0> (Configuration Word) SCS (OSCCON<0>)
External Oscillator OSC2 Sleep OSC1 IRCF<2:0> (OSCCON<6:4>) 8 MHz Internal Oscillator 4 MHz 2 MHz Postscaler 101 100 500 kHz 250 kHz 125 kHz LFINTOSC 31 kHz 31 kHz 011 010 001 000 MUX 1 MHz HFINTOSC 8 MHz 111 110
LP, XT, HS, RC, RCIO, EC MUX
System Clock (CPU and Peripherals)
Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
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Preliminary
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PIC16F785
3.2 Clock Source Modes 3.3
3.3.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
Clock source modes can be classified as external or internal. * External clock modes rely on external circuitry for the clock source. Examples are oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT, and HS modes), and resistor-capacitor (RC mode) circuits. * Internal clock sources are contained internally within the PIC16F785. The PIC16F785 has two internal oscillators; the 8 MHz High-frequency Internal Oscillator (HFINTOSC) and 31 kHz Low-frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 3.5 "Clock Switching").
When the PIC16F785 is configured for any of the crystal oscillator modes (LP, XT or HS), the Oscillator Start-up Timer (OST) is enabled, which extends the reset period to allow the oscillator additional time to stabilize. The OST counts 1024 clock periods present on the OSC1 pin following a Power-on Reset (POR), a wake from Sleep, or when the Power-up Timer (PWRT) has expired (if the PWRT is enabled). During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the PIC16F785. Table 3-1 shows examples where the oscillator delay is invoked. In order to minimize latency between external oscillator start-up and code execution, the Two-speed Clock Start-up mode can be selected (see Section 3.6 "Two-Speed Clock Start-up Mode").
TABLE 3-1:
Switch From Sleep/POR Sleep LFINTOSC (31 kHz) Sleep/POR LFINTOSC (31 kHz) Note 1:
OSCILLATOR DELAY EXAMPLES
Switch To INTRC INTOSC EC, RC EC, RC LP, XT, HS INTOSC Frequency 31 kHz 125 kHz-8 MHz DC - 20 MHz DC - 20 MHz 31 kHz-20 MHz 125 kHz-8 MHz 1024 Clock Cycles (OST) 1 s (approx.) 5 s-10 s (approx.) CPU Start-up(1) Oscillator Delay Comments
Following a wake-up from Sleep mode or POR, CPU start-up is invoked to allow the CPU to become ready for code execution.
The 5 s-10 s start-up delay is based on a 1 MHz System Clock.
3.3.2
EC MODE
FIGURE 3-2:
The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to OSC1 pin and the RA4 pin is available for general purpose I/O. Figure 3-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC16F785 design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC16F785 RA4 I/O (OSC2)
Clock from Ext. System
DS41249A-page 24
Preliminary
2004 Microchip Technology Inc.
PIC16F785
3.3.3 LP, XT, HS MODES FIGURE 3-4:
The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to the OSC1 and OSC2 pins (Figure 3-1). The mode selects a low, medium, or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. XT oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification, for example, AT-cut quartz crystal resonators. HS oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting, for example, AT-cut quartz crystal resonators or ceramic resonators. Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively.
CERAMIC RESONATOR OPERATION (XT OR HS MODE)
OSC1
PIC16F785
C1 RP(3) OSC2 RS(1) C2 Ceramic Resonator To Internal Logic RF(2) Sleep
Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the oscillator mode selected (typically between 2 M to 10 M). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation (typical value 1 M).
FIGURE 3-3:
QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
OSC1
PIC16F785
C1 Quartz Crystal OSC2 RS(1) C2 To Internal Logic RF(2) Sleep
Note 1: 2:
A series resistor (RS) may be required for quartz crystals with low drive level. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M).
Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 25
PIC16F785
3.3.4 EXTERNAL RC MODES
3.4
Internal Clock Modes
The External Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes, RC and RCIO. In RC mode, the RC circuit connects to the OSC1 pin. The OSC2/CLKOUT pin outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the RC mode connections.
The PIC16F785 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC (High-frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted 12% via software using the OSCTUNE register (Register 3-1). The LFINTOSC (Low-frequency Internal Oscillator) is uncalibrated and operates at approximately 31 kHz.
2.
FIGURE 3-5:
VDD REXT
RC MODE
The system clock speed can be selected via software using the Internal Oscillator Frequency Select (IRCF) bits.
Internal Clock PIC16F785
OSC1 CEXT VSS
The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (See Section 3.5 "Clock Switching").
3.4.1
INTRC AND INTRCIO MODES
OSC2/CLKOUT FOSC/4 Recommended values: 3 k REXT 100 k (VDD 3V) 10 k REXT 100 k (VDD < 3V) CEXT > 20 pF
The INTRC and INTRCIO modes configure the internal oscillators as the system clock source when the device is programmed using the Oscillator Selection (FOSC) bits in the Configuration Word (Register 12-1). In INTRC mode, the OSC1 pin is available for general purpose I/O. The OSC2/CLKOUT pin outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTRCIO mode, the OSC1 and OSC2 pins are available for general purpose I/O.
In RCIO mode, the RC circuit is connected to the OSC1 pin. The OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 4 of PORTA (RA4). Figure 3-6 shows the RCIO mode connections.
FIGURE 3-6:
VDD REXT
RCIO MODE
3.4.2
OSC1 CEXT VSS RA4 I/O (OSC2) PIC16F785 Internal Clock
HFINTOSC
The High-frequency Internal Oscillator (HFINTOSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered approximately 12% via software using the OSCTUNE register (Register 3-1). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven frequencies can be selected via software using the IRCF bits (see Section 3.4.4 "Frequency Select Bits (IRCF)"). The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz (IRCF 000) as the system clock source (SCS = 1) or when Two-Speed Start-up is enabled (IESO = 1 and IRCF 000). The HF Internal Oscillator (HTS) bit, (OSCCON<2>), indicates whether the HFINTOSC is stable or not.
Recommended values: 3 k REXT 100 k (VDD 3V) 10 k REXT 100 k (VDD < 3V) CEXT > 20 pF
The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal threshold voltage. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency or low CEXT values. The user also needs to take into account variation due to tolerance of external RC components used.
DS41249A-page 26
Preliminary
2004 Microchip Technology Inc.
PIC16F785
3.4.2.1 Calibration Bits 3.4.2.2 OSCTUNE Register
The 8 MHz High-frequency Internal Oscillator (HFINTOSC) is factory calibrated. The HFINTOSC calibration bits are stored in the Calibration Word (CALIB) located in program memory location 2008h. The calibration word is not erased using the specified bulk erase sequence in the PIC16F785 Memory Programming Specification (DS41237) and does not require reprogramming. For more information on the Calibration Word register (See Section 15.2 "Calibration Bits"). The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-1). The OSCTUNE register has a tuning range of 12%. The default value of the OSCTUNE register is `0'. The value is a 5-bit two's complement number. Due to process variation, the monotonicity and frequency step cannot be specified. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. The HFINTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.
Note:
Address 2008h is beyond the user program memory space. It belongs to the special Configuration Memory space (2000h - 3FFFh), which can be accessed only during programming. See PIC16F785 Memory Programming Specification (DS41237) for more information.
REGISTER 3-1:
OSCTUNE -- OSCILLATOR TUNING RESISTOR (ADDRESS 90h)
U-0 -- bit 7 U-0 -- U-0 -- R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
bit 7-5 bit 4-0
Unimplemented: Read as `0' TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = * * * 00001 = 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 = * * * 10000 = Minimum frequency Legend: R = Readable bit - n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 27
PIC16F785
3.4.3 LFINTOSC 3.4.5
The Low-frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 "Frequency Select Bits (IRCF)"). The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF = 000) as the system clock source (SCS = 1), or when any of the following are enabled: * * * * Two-Speed Start-up (IESO = 1 and IRCF = 000) Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
HF AND LF INTOSC CLOCK SWITCH TIMING
When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power. If this is the case, there is a 10 s delay after the IRCF bits are modified before the frequency selection takes place. The LTS/HTS bits will reflect the current active status of the LFINTOSC and the HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. IRCF bits are modified. If the new clock is shut down, a 10 s clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. CLKOUT is held low and the clock switch circuitry waits for a rising edge in the new clock. CLKOUT is now connected with the new clock. HTS/LTS bits are updated as required. Clock switch is complete.
The LF Internal Oscillator (LTS) bit, (OSCCON<1>), indicates whether the LFINTOSC is stable or not.
3.4.4
FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connect to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency select bits IRCF<2:0> (OSCCON<6:4>) select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: * * * * * * * * 8 MHz 4 MHz (Default after Reset) 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz
If the internal oscillator speed selected is between 8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and the new frequencies are derived from the HFINTOSC via the postscaler and multiplexer. Note: Care must be taken to ensure an invalid voltage or frequency selection is not selected. An example of an invalid configuration is selecting 8 MHz when VDD is 2.0V.
Note:
Following any Reset, the IRCF bits are set to `110' and the frequency selection is forced to 4 MHz. The user can modify the IRCF bits to select a different frequency.
DS41249A-page 28
Preliminary
2004 Microchip Technology Inc.
PIC16F785
3.5 Clock Switching
The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit. When the PIC16F785 is configured for LP, XT, or HS modes, the Oscillator Start-up Timer (OST) is enabled (See Section 3.3.1 "Oscillator Start-up Timer (OST)"). The OST timer will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit (OSCCON<3>) is set, program execution switches to the external oscillator.
3.5.1
SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit, (OSCCON<0>), selects the system clock source that is used for the CPU and peripherals. * When SCS = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in Configuration Word (CONFIG). * When SCS = 1, the system clock source is chosen by the internal oscillator frequency selected by the IRCF bits. After a Reset, SCS is always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bit. The user can monitor the OSTS (OSCCON<3>) to determine the current system clock source.
3.6.1
TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode is configured by the following settings: * IESO = 1 (CONFIG<10>) Internal/External Switch Over bit. * SCS = 0. * FOSC configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after PWRT has expired, or * Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.
3.5.2
OSCILLATOR START-UP TIME-OUT STATUS BIT
The Oscillator Start-up Time-out Status (OSTS) bit, (OSCCON<3>), indicates whether the system clock is running from the external clock source as defined by the FOSC bits, or from internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes.
3.6.2
1. 2.
TWO-SPEED START-UP SEQUENCE
3.6
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the Oscillator Start-up Time and will cause the OSTS bit (OSCCON<3>) to remain clear.
3. 4. 5. 6. 7.
Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF bits (OSCCON<6:4>). OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
3.6.3
CHECKING EXTERNAL/INTERNAL CLOCK STATUS
Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC16F785 is running from the external clock source as defined by the FOSC bits in the Configuration Word (CONFIG) or the internal oscillator.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 29
PIC16F785
FIGURE 3-7: TWO-SPEED START-UP
Q1 INTOSC T TOST OSC1 0 1 1022 1023 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC2 Program Counter PC PC + 1 PC + 2
System Clock
3.7
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired.
The frequency of the internal oscillator will depend upon the value contained in the IRCF bits (OSCCON<6:4>). Upon entering the Fail-Safe condition, the OSTS bit (OSCCON<3>) is automatically cleared to reflect that the internal oscillator is active and the WDT is cleared. The SCS bit (OSCCON<0>) is not updated. Enabling FSCM does not affect the LTS bit. The FSCM sample clock is generated by dividing the LFINTOSC clock by 64. This will allow enough time between FSCM sample clocks for a system clock edge to occur. Figure 3-8 shows the FSCM block diagram. On the rising edge of the sample clock, the monitoring latch (CM = 0) will be cleared. On a falling edge of the primary system clock, the monitoring latch will be set (CM = 1). In the event that a falling edge of the sample clock occurs, and the monitoring latch is not set, a clock failure has been detected. The assigned internal oscillator is enabled when FSCM is enabled as reflected by the IRCF bits. Note:
FIGURE 3-8:
FSCM BLOCK DIAGRAM
Clock Monitor Latch (CM) (edge-triggered)
Primary Clock
S
Q
LFINTOSC Oscillator 31 kHz (~32 s)
/ 64 488 Hz (~2 ms)
C
Q
Clock Failure Detected
Two-Speed Start-up is automatically enabled when the Fail-Safe Clock Monitor mode is enabled.
The FSCM function is enabled by setting the FCMEN bit in Configuration Word (CONFIG). It is applicable to all external clock options (LP, XT, HS, EC, RC or I/O modes). In the event of an external clock failure, the FSCM will set the OSFIF bit (PIR1<2>) and generate an oscillator fail interrupt if the OSFIE bit (PIE1<2>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited.
DS41249A-page 30
Preliminary
2004 Microchip Technology Inc.
PIC16F785
3.7.1 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction, or a modification of the SCS bit. While in Fail-Safe condition, the PIC16F785 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON<6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
FIGURE 3-9:
Sample Clock System Clock Output CM Output (Q)
FSCM TIMING DIAGRAM
Oscillator Failure
Failure Detected OSCFIF
CM Test
CM Test
CM Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
3.7.2
RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired. If the external clock is EC or RC mode, monitoring will begin immediately following these events. For LP, XT or HS mode, the external oscillator may require a start-up time considerably longer than the FSCM sample clock time; a false clock failure may be detected (See Figure 3-9). To prevent this, the internal oscillator is automatically configured as the system clock and functions until the external clock is stable (the OST has timed out). This is identical to Two-Speed Start-up mode. Once the external oscillator is stable, the LFINTOSC returns to its role as the FSCM source. Note: Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit (OSCCON<3>) to verify the oscillator start-up and system clock switchover has successfully completed.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 31
PIC16F785
REGISTER 3-2: OSCCON -- OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)
U-0 -- bit 7 bit 7 bit 6-4 R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 R-q OSTS(1) R-0 HTS R-0 LTS R/W-0 SCS bit 0
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' IRCF<2:0>: Internal Oscillator Frequency Select bits 000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz 101 = 2 MHz 110 = 4 MHz 111 = 8 MHz OSTS: Oscillator Start-up Time-out Status bit 1 = Device is running from the external system clock defined by FOSC<2:0> 0 = Device is running from the internal system clock (HFINTOSC or LFINTOSC) HTS: HFINTOSC (High Frequency - 8 MHz to 125 kHz) Status bit 1 = HFINTOSC is stable 0 = HFINTOSC is not stable LTS: LFINTOSC (Low Frequency - 31 kHz) Stable bit 1 = LFINTOSC is stable 0 = LFINTOSC is not stable SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> Note 1: Bit resets to `0' with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled, otherwise this bit resets to `1'. Legend: q = value depends on condition R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown
TABLE 3-2:
Address
0Ch 8Ch 8Fh 90h 2007h(1) Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name Bit 7
EEIF EEIE -- -- CPD
Bit 6
ADIF ADIE IRCF2 -- CP
Bit 5
CCP1IF CCP1IE IRCF1 -- MCLRE
Bit 4
C2IF C2IE IRCF0 TUN4 PWRTE
Bit 3
C1IF C1IE OSTS TUN3 WDTE
Bit 2
OSFIF OSFIE HTS TUN2 FOSC2
Bit 1
TMR2IF TMR2IE LTS TUN1 FOSC1
Bit 0
TMR1IF TMR1IE SCS TUN0 FOSC0
Value on: POR, BOR
0000 0000 0000 0000 -110 q000 ---0 0000 --
Value on all other Resets
0000 0000 0000 0000 -110 q000 ---u uuuu --
PIR1 PIE1 OSCCON OSCTUNE CONFIG
x = unknown, u = unchanged, -- = unimplemented locations read as `0', q= value depends on condition. Shaded cells are not used by oscillators. See Register 15-1 for operation of all Configuration Word bits.
DS41249A-page 32
Preliminary
2004 Microchip Technology Inc.
PIC16F785
4.0 I/O PORTS
There are seventeen general purpose I/O pins and one input only pin available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Note: Additional information on I/O ports may be found in the PICmicro(R) Mid-Range Reference Manual (DS33023). The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. When RA1 is configured as a voltage reference output, the RA1 digital output driver will automatically be disabled while not affecting the TRISA<1> value. Note: The ANSEL0 (91h) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
4.1
PORTA and TRISA Registers
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 4-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as `1'. Example 4-1 shows how to initialize PORTA. Reading the PORTA register (Register 4-1) reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read; this value is modified and then written to the port data latch. RA3 reads `0' when MCLRE = 1.
EXAMPLE 4-1:
BCF BCF CLRF MOVLW ANDWF BSF MOVLW MOVWF BCF
INITIALIZING PORTA
;Bank 0 ; ;Init PORTA ;Set RA<2:0> to ; digital I/O ;Bank 1 ;Set RA<3:2> as inputs ; and set RA<5:4,1:0> ; as outputs ;Bank 0
STATUS,RP0 STATUS,RP1 PORTA F8h ANSEL0,f STATUS,RP0 0Ch TRISA STATUS,RP0
REGISTER 4-1:
PORTA -- PORTA REGISTER (ADDRESS: 05h, 105h)
U-0 -- bit 7 U-0 -- R/W-x RA5 R/W-x(1) RA4 R/W-x RA3 R/W-x(1) RA2 R/W-x(1) RA1 R/W-x(1) RA0 bit 0
bit 7-6: bit 5-0:
Unimplemented: Read as `0' RA<5:0>: PORTA I/O pin 1 = Port pin is >VIH 0 = Port pin is 2004 Microchip Technology Inc.
Preliminary
DS41249A-page 33
PIC16F785
REGISTER 4-2: TRISA -- PORTA TRISTATE REGISTER (ADDRESS: 85h, 185h)
U-0 -- bit 7 bit 7-6: bit 5-0: Unimplemented: Read as `0' TRISA<5:0>: PORTA Tri-State Control bit(1)(2) 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: 2: Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as `0' 0 = Bit is cleared x = Bit is unknown TRISA<3> always reads `1'. TRISA<5:4> always reads `1' in XT, HS and LP OSC modes. U-0 -- R/W-1 TRISA5 R/W-1 TRISA4 R-1 TRISA3 R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0 bit 0
4.2
Additional Pin Functions
4.2.1 WEAK PULL-UPS
Each of the PORTA pins has an individually configurable internal weak pull-up. Control bits WPUAx enable or disable each pull-up. Refer to Register 4-3. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the RAPU bit (OPTION_REG<7>). The weak pull-up on RA3 is automatically enabled when RA3 is configured as MCLR.
Every PORTA pin on the PIC16F785 has an interrupton-change option and a weak pull-up option. The next three sections describe these functions.
REGISTER 4-3:
WPUA -- WEAK PULL-UP REGISTER (ADDRESS: 95h)(1,2)
U-0 -- bit 7 U-0 -- R/W-1 R/W-1 R/W-1 R/W-1 WPUA2 R/W-1 WPUA1 R/W-1 WPUA0 bit 0 WPUA5(4) WPUA4(4) WPUA3(3)
bit 7-6 bit 5-0
Unimplemented: Read as `0' WPUA<5:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: 3: 4: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Global RAPU must be enabled for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0). The RA3 pull-up is automatically enabled when configured as MCLR in the Configuration Word. WPUA<5:4> always reads `1' in XT, HS and LP OSC modes.
DS41249A-page 34
Preliminary
2004 Microchip Technology Inc.
PIC16F785
4.2.2 INTERRUPT-ON-CHANGE
Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits IOCAx enable or disable the interrupt function for each pin. Refer to Register 4-4. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA. The `mismatch' outputs of the last read are OR'd together to set, the PORTA Change Interrupt flag bit (RAIF) in the INTCON register (Register 2-3). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) b) Any read or write of PORTA. This will end the mismatch condition, then, Clear the flag bit RAIF.
A mismatch condition will continue to set flag bit RAIF. Reading PORTA will end the mismatch condition and allow flag bit RAIF to be cleared. The latch holding the last read value is neither affected by an MCLR nor BOR Reset. After these resets, the RAIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.
REGISTER 4-4:
IOCA -- INTERRUPT-ON-CHANGE PORTA REGISTER (ADDRESS: 96h)(1)
U-0 -- bit 7 U-0 -- R/W-0 IOCA5 R/W-0 IOCA4 R/W-0 IOCA3 R/W-0 IOCA2 R/W-0 IOCA1 R/W-0 IOCA0 bit 0
bit 7-6 bit 5-0
Unimplemented: Read as `0' IOCA<5:0>: Interrupt-on-change PORTA Control bits(2) 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads `1' in XT, HS and LP OSC modes. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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Preliminary
DS41249A-page 35
PIC16F785
4.2.3 PORTA PIN DESCRIPTIONS AND DIAGRAMS 4.2.3.2 RA1/AN1/C12IN0-/VREF/ICSPCLK
Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. Figure 4-1 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: * * * * * * a general purpose I/O an analog input for the A/D an analog input to comparators 1 & 2 a voltage reference input for the A/D a buffered or unbuffered voltage reference output In-Circuit Serial Programming clock
4.2.3.1
RA0/AN0/C1IN+/ICSPDAT
Figure 4-1 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following: * * * * a general purpose I/O an analog input for the A/D an analog input to comparator 1 In-Circuit Serial ProgrammingTM data
FIGURE 4-2:
VROUT VROE*VREN CVROE ANS1 DATA BUS WR WPUA RD WPUA D WR PORTA Q D Q
BLOCK DIAGRAM OF RA1
FIGURE 4-1:
DATA BUS WR WPUA RD WPUA D Q
BLOCK DIAGRAM OF RA0
ANS0 VDD WEAK RAPU
VDD WEAK
CK Q
RAPU
CK Q
VDD
CK Q I/O PIN D Q VSS
D WR PORTA
Q
VDD
CK Q I/O PIN D Q VSS ANS0 RD TRISA RD PORTA WR TRISA
CK Q
WR TRISA RD TRISA RD PORTA
CK Q
Q D Q
D EN
Q D Q
D EN
WR IOCA RD IOCA
CK Q Q D EN Q D Q3 EN RD PORTA TO COMPARATORS TO A/D CONVERTER Q1
WR IOCA RD IOCA
CK Q Q D EN Q D Q3 EN RD PORTA Q1
INTERRUPT-ONCHANGE
INTERRUPT-ONCHANGE
TO COMPARATOR TO A/D CONVERTER
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Preliminary
2004 Microchip Technology Inc.
PIC16F785
4.2.3.3 RA2/AN2/T0CKI/INT/C1OUT 4.2.3.4 RA3/MCLR/VPP
Figure 4-3 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D the clock input for TMR0 an external edge triggered interrupt a digital output from comparator 1 Figure 4-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: * a general purpose input * as Master Clear Reset w/weak pull-up
FIGURE 4-4:
DATA BUS WR WPUA RD WPUA D CK Q Q
BLOCK DIAGRAM OF RA3
MCLRE VDD
FIGURE 4-3:
C1OE C1OUT
BLOCK DIAGRAM OF RA2
WEAK RAPU RESET VSS MCLRE VSS MCLRE INPUT PIN
ANS2 DATA BUS WR WPUA RD WPUA D WR PORTA CK Q Q 1 0 D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA Q INTERRUPT-ONCHANGE TO TMR0 TO INT TO A/D CONVERTER CK Q EN Q Q D EN D CK Q D CK Q Q
VDD WEAK
RD TRISA RD PORTA D WR IOCA CK Q
RAPU
Q Q
D EN
VDD
RD IOCA
Q
D EN Q1
I/O PIN
INTERRUPT-ONCHANGE
Q
D Q3 EN
Q ANS2
VSS RD PORTA
Q
D
Q1
Q3 EN RD PORTA
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Preliminary
DS41249A-page 37
PIC16F785
4.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT 4.2.3.6 RA5/T1CKI/OSC1/CLKIN
Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D a TMR1 gate input a crystal/resonator connection a clock output Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: * * * * a general purpose I/O a TMR1 clock input a crystal/resonator connection a clock input
FIGURE 4-6: FIGURE 4-5:
DATA BUS WR WPUA RD WPUA
BLOCK DIAGRAM OF RA5
INTOSC MODE
BLOCK DIAGRAM OF RA4
ANS3 CLK(1) MODES VDD WEAK RAPU OSCILLATOR CIRCUIT OSC1 FOSC/4 1 0 CLKOUT ENABLE INTOSC/ RC/EC(2) VSS WR TRISA RD TRISA (2) ANS3 RD PORTA D Q Q Q Q D EN D EN Q Q D Q3 EN RD PORTA RD PORTA TO TMR1 OR CLKGEN D Q3 EN Q1 I/O PIN WR PORTA VDD RD WPUA DATA BUS WR WPUA D CK Q Q RAPU OSCILLATOR CIRCUIT OSC2 D CK Q I/O PIN Q VSS DSQ CK Q INTOSC MODE CLKOUT ENABLE VDD CLK MODES(1) VDD WEAK
D CK
Q Q
D WR PORTA CK
Q Q
D SQ WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA CK Q Q Q Q D EN D EN Q1 CK Q
WR IOCA RD IOCA
CK
INTERRUPT-ONCHANGE
INTERRUPT-ONCHANGE
TO T1G TO A/D CONVERTER Note Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option. 1: CLK modes are XT, HS, LP and LPTMR1. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed.
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Preliminary
2004 Microchip Technology Inc.
PIC16F785
TABLE 4-1:
Addr
05h, 105h 10h 0Bh, 8Bh 81h, 181h 85h, 185h 91h 95h 96h 98h 119h 11Bh Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
-- T1GINV GIE RAPU -- ANS7 -- -- -- C1ON
Name
PORTA T1CON INTCON OPTION_REG TRISA ANSEL0 WPUA IOCA REFCON CM1CON0 CM2CON1
Bit 6
--
Bit 5
RA5
Bit 4
RA4
Bit 3
RA3
Bit 2
RA2
Bit 1
RA1
Bit 0
RA0
Value on: POR, BOR
--xx xxxx 0000 0000 0000 0000 1111 1111 --11 1111 1111 1111 --11 1111 --00 0000 --00 0000000 0000 00-- --10
Value on all other Resets
--uu uuuu 0000 0000 0000 0000 1111 1111 --11 1111 1111 1111 --11 1111 --00 0000 --00 0000000 0000 00-- --10
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON PEIE INTEDG -- ANS6 -- -- -- C1OUT T0IE T0CS TRISA5 ANS5 WPUA5 IOCA5 BGST C1OE -- INTE T0SE TRISA4 ANS4 WPUA4 IOCA4 VRBB C1POL -- RAIE PSA TRISA3 ANS3 WPUA3 IOCA3 VREN C1SP -- T0IF PS2 TRISA2 ANS2 WPUA2 IOCA2 VROE C1R -- INTF PS1 TRISA1 ANS1 WPUA1 IOCA1 CVROE C1CH1 T1GSS RAIF PS0 TRISA0 ANS0 WPUA0 IOCA0 -- C1CH0 C2SYNC
MC1OUT MC2OUT
x = unknown, u = unchanged, -- = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 39
PIC16F785
4.3 PORTB and TRISB Registers
PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 4-6). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Example 4-2 shows how to initialize PORTB. Reading the PORTB register (Register 4-5) reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. Pin RB6 is an open drain output. All other PORTB pins have full CMOS output drivers. The TRISB register controls the direction of the PORTB pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSEL1 (93h) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
EXAMPLE 4-2:
BCF BCF CLRF BSF BCF BCF MOVLW MOVWF BCF STATUS,RP0 STATUS,RP1 PORTB STATUS,RP0 ANSEL1,2 ANSEL1,3 30h TRISB STATUS,RP0
INITIALIZING PORTB
;Bank 0 ; ;Init PORTB ;Bank 1 ;digital I/O - RB4 ;digital I/O - RB5 ;Set RB<5:4> as inputs ;and set RB<7:6> ;as outputs ;Bank 0
REGISTER 4-5:
PORTB -- PORTB REGISTER (ADDRESS: 06h, 106h)
R/W-x RB7 bit 7 R/W-x RB6 R/W-x(1) RB5 R/W-x(1) RB4 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7-4:
RB<7:4>: PORTB General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL Unimplemented: Read as "0" Note 1: Data latches are unknown after a POR, but each port bit reads `0' when the corresponding analog select bit is `1' (see Register 12-2 on page 80). Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3-0:
REGISTER 4-6:
TRISB -- PORTB TRISTATE REGISTER (ADDRESS: 86h, 186h)
R/W-1 TRISB7 bit 7 R/W-1 TRISB6 R/W-1 TRISB5 R/W-1 TRISB4 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7-4:
TRISB<7:4>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output Unimplemented: Read as "0" Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3-0
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Preliminary
2004 Microchip Technology Inc.
PIC16F785
4.3.1 PORTB PIN DESCRIPTIONS AND DIAGRAMS
4.3.1.3 RB6 Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the PWM, operational amplifier, or the A/D, refer to the appropriate section in this Data Sheet. 4.3.1.1 RB4/AN10/OP2D WR PORTB CK Q Q N D WR TRISB RD TRISB Q D EN RD PORTB CK Q Q VSS VSS I/O PIN
The RB6 pin is configurable to function as the following: * an open drain general purpose I/O
FIGURE 4-8:
DATA BUS
BLOCK DIAGRAM OF RB6
The RB4/AN10/OP2- pin is configurable to function as one of the following: * a general purpose I/O * an analog input to the A/D * an analog input to Op Amp 2 4.3.1.2 RB5/AN11/OP2+
The RB5/AN11/OP2+ pin is configurable to function as one of the following: * a general purpose I/O * an analog input to the A/D * an analog input to Op Amp 2
FIGURE 4-7:
DATA BUS
BLOCK DIAGRAM OF RB4 AND RB5
4.3.1.4
RB7/SYNC
The RB7/SYNC pin is configurable to function as one of the following:
Q Q VDD
D WR PORTB CK
* a general purpose I/O * PWM synchronization input and output
FIGURE 4-9:
I/O PIN D WR TRISB RD TRISB Q CK Q Q ANS10 (RB4) ANS11 (RB5) VSS PH1EN PH2EN PWM MASTER SYNC OUT DATA BUS
BLOCK DIAGRAM OF RB7
D EN WR PORTB
D CK
Q Q 1 0
VDD
RD PORTB TO A/D CONVERTER TO OP AMP2 WR TRISB RD TRISB Q D EN RD PORTB TO PWM SYNC INPUT D CK Q Q
I/O PIN
VSS
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Preliminary
DS41249A-page 41
PIC16F785
TABLE 4-2:
Address
06h, 106h 86h, 186h 93h 111h 11Dh Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7
RB7 TRISB7 -- PRSEN OPAON
Bit 6
RB6 TRISB6 -- PASEN --
Bit 5
RB5 TRISB5 -- BLANK2 --
Bit 4
RB4 TRISB4 -- BLANK1 --
Bit 3
-- -- ANS11 SYNC1 --
Bit 2
-- -- ANS10 SYNC0 --
Bit 1
-- -- ANS9 PH2EN --
Bit 0
-- -- ANS8 PH1EN --
Value on: POR, BOR
xxxx ---1111 ------- 1111 0000 0000 0--- ----
Value on all other Resets
uuuu ---1111 ------- 1111 0000 0000 0--- ----
PORTB TRISB ANSEL1 PWMCON0 OPA2CON
x = unknown, u = unchanged, -- = unimplemented locations read as `0'. Shaded cells are not used by PORTB.
DS41249A-page 42
Preliminary
2004 Microchip Technology Inc.
PIC16F785
4.4 PORTC and TRISC Registers
PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 4-8). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). Example 4-3 shows how to initialize PORTC. Reading the PORTC register (Register 4-7) reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. The TRISC register controls the direction of the PORTC pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. When RC4 or RC5 is configured as an op amp output, the corresponding RC4 or RC5 digital output driver will automatically be disabled regardless of the TRISC<4> or TRISC<5> value.
Note:
The ANSEL0 (91h) and ANSEL1 (93h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
EXAMPLE 4-3:
BCF BCF CLRF BSF CLRF CLRF MOVLW MOVWF BCF STATUS,RP0 STATUS,RP1 PORTC STATUS,RP0 ANSEL0 ANSEL1 0Ch TRISC STATUS,RP0
INITIALIZING PORTC
;Bank 0 ;Init PORTC ;Bank 1 ;digital I/O ;digital I/O ;Set RC<3:2> as inputs ; and set RC<5:4,1:0> ; as outputs ;Bank 0
REGISTER 4-7:
PORTC -- PORTC REGISTER (ADDRESS: 07h, 107h)
R/W-x(1) RC7 bit 7 R/W-x(1) RC6 R/W-x RC5 R/W-x RC4 R/W-x(1) RC3 R/W-x(1) RC2 R/W-x(1) RC1 R/W-x(1) RC0 bit 0
bit 7-0:
RC<7:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is greater than VIH 0 = Port pin is less than VIL Note 1: Data latches are unknown after a POR, but each port bit reads `0' when the corresponding analog select bit is `1' (see Register 12-1 and Register 12-2 on page 80). Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 4-8:
TRISC -- PORTC TRISTATE REGISTER (ADDRESS: 87h, 187h)
R/W-1 TRISC7 bit 7 R/W-1 TRISC6 R/W-1 TRISC5 R/W-1 TRISC4 R/W-1 TRISC3 R/W-1 TRISC2 R/W-1 TRISC1 R/W-1 TRISC0 bit 0
bit 7-0:
TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 43
PIC16F785
4.4.1 PORTC PIN DESCRIPTIONS AND DIAGRAMS 4.4.1.4 RC1/AN5/C12IN1-/PH1
Each PORTC pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. The RC1 is configurable to function as one of the following: * * * * a general purpose I/O an analog input for the A/D Converter an analog input to comparators 1 & 2 a digital output from the Two-Phase PWM
4.4.1.1
RC0/AN4/C2IN+ FIGURE 4-11:
PH1EN PH1 DATA BUS D WR PORTC CK Q Q VDD
The RC0 is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D Converter * the non-inverting input to comparator 2
BLOCK DIAGRAM OF RC1
4.4.1.2
RC6/AN8/OP1-
The RC6/AN8/OP1- pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D * the inverting input for Op Amp 1
1 0 I/O PIN
D WR TRISC RD TRISC CK
Q Q ANS5 VSS
4.4.1.3
RC7/AN9/OP1+
The RC7/AN9/OP1+ pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D * the non-inverting input for Op Amp 1
Q
D EN
RD PORTC TO COMPARATORS TO A/D CONVERTER
FIGURE 4-10:
DATA BUS
BLOCK DIAGRAM OF RC0, RC6 AND RC7
D WR PORTC CK
Q Q
VDD
I/O PIN D WR TRISC RD TRISC Q CK Q Q ANS4 (RC0) ANS8 (RC6) ANS9 (RC7) D EN RD PORTC TO COMPARATORS (RC0) TO A/D CONVERTER TO OP AMP1 (RC6, RC7) VSS
DS41249A-page 44
Preliminary
2004 Microchip Technology Inc.
PIC16F785
4.4.1.5 RC2/AN6/C12IN2-/OP2 4.4.1.7 RC4/C2OUT/PH2
The RC2 is configurable to function as one of the following: * * * * a general purpose I/O an analog input for the A/D Converter an analog input to comparators 1 & 2 an analog output from Op Amp 2 The RC4 is configurable to function as one of the following: * a general purpose I/O * a digital output from comparator 2 * a digital output from the Two-Phase PWM
4.4.1.6
RC3/AN7/C12IN3-/OP1
FIGURE 4-13:
C2OE PH2EN PH2 C2OUT DATA BUS 1 0
BLOCK DIAGRAM OF RC4
The RC3 is configurable to function as one of the following: * * * * a general purpose I/O an analog input for the A/D Converter an analog input to comparators 1 & 2 an analog output for Op Amp 1
FIGURE 4-12:
OPAMP OUT OPAON DATA BUS
BLOCK DIAGRAM OF RC2 AND RC3
D WR PORTC
Q 1 0
VDD
CK Q
I/O PIN
D
VDD
Q VSS
D WR PORTC CK
Q Q
WR TRISC RD TRISC
I/O PIN
CK Q
Q
D EN
D WR TRISC RD TRISC CK
Q Q ANS6 (RC2) ANS7 (RC3) VSS
RD PORTC
Q
D EN
RD PORTC TO COMPARATORS TO A/D CONVERTER
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 45
PIC16F785
4.4.1.8 RC5/CCP1 FIGURE 4-14:
CCP1CON<1> CCP1CON<3> CCP1CON<2> CCP OUT DATA BUS D WR PORTC CK Q Q 1 0 D WR TRISC RD TRISC Q D EN RD PORTC TO CCP CAPTURE INPUT CK Q Q VSS I/O PIN VDD
The RC5 is configurable to function as one of the following: * a general purpose I/O * a digital input for the capture/compare * a digital output for the CCP
BLOCK DIAGRAM OF RC5 PIN
TABLE 4-3:
Address
07h, 107h 15h 87h, 187h 91h 93h 111h 11Ch 11Dh Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7
RC7 -- TRISC7 ANS7 -- PRSEN OPAON OPAON
Bit 6
RC6 -- TRISC6 ANS6 -- PASEN -- --
Bit 5
RC5 DC1B1 TRISC5 ANS5 -- BLANK2 -- --
Bit 4
RC4 DC1B0 TRISC4 ANS4 -- BLANK1 -- --
Bit 3
RC3
Bit 2
RC2
Bit 1
RC1
Bit 0
RC0
Value on: POR, BOR
xxxx xxxx 0000 0000 1111 1111 1111 1111 ---- 1111 0000 0000 0--- ---0--- ----
Value on all other Resets
uuuu uuuu 0000 0000 1111 1111 1111 1111 ---- 1111 0000 0000 0--- ---0--- ----
PORTC CCP1CON TRISC ANSEL0 ANSEL1 PWMCON0 OPA1CON OPA2CON
CCP1M3 CCP1M2 CCP1M1 CCP1M0 TRISC3 ANS3 ANS11 SYNC1 -- -- TRISC2 ANS2 ANS10 SYNC0 -- -- TRISC1 ANS1 ANS9 PH2EN -- -- TRISC0 ANS0 ANS8 PH1EN -- --
x = unknown, u = unchanged, -- = unimplemented locations read as `0'. Shaded cells are not used by PORTC.
DS41249A-page 46
Preliminary
2004 Microchip Technology Inc.
PIC16F785
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin RA2/AN2/T0CKI/INT/C1OUT. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the rising edge. Note 1: Counter mode has specific external clock requirements. Additional information on these requirements is available in the PICmicro(R) Mid-Range Reference Manual, (DS33023). 2: The ANSEL0 (91h) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. Note: Additional information on the Timer0 module is available in the PICmicro(R) Mid-Range Reference Manual, (DS33023).
5.2 5.1 Timer0 Operation
Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut-off during Sleep.
FIGURE 5-1:
CLKOUT (= FOSC/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 8 1 1 0 0 8-bit Prescaler 1 8 PSA(1) SYNC 2 Cycles TMR0
RA2/AN2/T0CKI/INT/C1OUT
T0SE(1)
T0CS(1)
Set Flag bit T0IF on Overflow
WDTE SWDTEN
PSA(1)
PS<0:2>(1) 16-bit Prescaler 31 kHz INTRC Watchdog Timer WDTPS<3:0>(2)
1 WDT Time-out 0
16 PSA(1)
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG (see Register 2-2 on page 16). 2: WDTPS<3:0> are bits in the WDTCON register (see Register 15-2 on page 118).
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 47
PIC16F785
5.3 Using Timer0 with an External Clock
(Example 5-2 and Example 5-3) must be executed when changing the prescaler assignment between Timer0 and WDT.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
EXAMPLE 5-2:
BCF STATUS,RP0 BCF STATUS,RP1 CLRWDT CLRF TMR0 BSF STATUS,RP0
CHANGING PRESCALER (TIMER0WDT)
;Bank 0 ; ;Clear WDT ;Clear TMR0 and ; prescaler ;Bank 1 ;Required if desired ; PS2:PS0 is ; 000 or 001 ; ;Set postscaler to ; desired WDT rate ;Bank 0
5.4
Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. For simplicity, this counter will be referred to as "prescaler" throughout this Data Sheet. The prescaler assignment is controlled in software by the control bit PSA (OPTION_REG<3>). Clearing the PSA bit will assign the prescaler to Timer0. Prescale values are selectable via the PS<2:0> bits (OPTION_REG<2:0>). The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer.
MOVLW b'00101111' MOVWF OPTION_REG CLRWDT MOVLW MOVWF BCF b'00101xxx' OPTION_REG STATUS,RP0
To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example 5-3. This precaution must be taken even if the WDT is disabled.
EXAMPLE 5-3:
CLRWDT BSF BCF MOVLW STATUS,RP0 STATUS,RP1
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ; prescaler ;Bank 1 ; ;Select TMR0, ; prescale, and ; clock source ; ;Bank 0
5.4.1
SWITCHING PRESCALER ASSIGNMENT
b'xxxx0xxx'
The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device Reset, the following instruction sequence
MOVWF BCF
OPTION_REG STATUS,RP0
TABLE 5-1:
Addr 01h, 101h 0Bh, 8Bh 81h, 181h 91h 85h, 185h Name
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets uuuu uuuu 0000 0000 1111 1111 1111 1111 --11 1111
TMR0 INTCON OPTION_REG ANSEL0 TRISA
Timer0 Module register GIE RAPU ANS7 -- PEIE INTEDG ANS6 -- T0IE T0CS ANS5 INTE T0SE ANS4 RAIE PSA ANS3 T0IF PS2 ANS2 INTF PS1 ANS1 RAIF PS0 ANS0
xxxx xxxx 0000 0000 1111 1111 1111 1111
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111
Legend:
-- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
DS41249A-page 48
Preliminary
2004 Microchip Technology Inc.
PIC16F785
6.0 TIMER1 MODULE WITH GATE CONTROL
The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module. Note: Additional information on timer modules is available in the PICmicro(R) Mid-Range Reference Manual, (DS33023).
The Timer1 module is the 16 bit counter of the PIC16F785. Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: 16-bit timer/counter (TMR1H:TMR1L) Readable and writable Internal or external clock selection Synchronous or asynchronous operation Interrupt on overflow from FFFFh to 0000h Wake-up upon overflow (Asynchronous mode) Optional external enable input - Selectable gate source; T1G or C2 output (T1GSS) - Selectable gate polarity (T1GINV) * Optional LP oscillator * * * * * * *
FIGURE 6-1:
TIMER1 ON THE PIC16F785 BLOCK DIAGRAM
TMR1ON TMR1GE TMR1ON TMR1GE TMR1(1) TMR1H TMR1L To C2 Comparator Module TMR1 Clock 0 Synchronized clock input T1GINV
Set flag bit TMR1IF on Overflow
RA5/T1CKI/OSC1/CLKIN
OSCILLATOR * 1 FOSC/4 Internal Clock
1 T1SYNC Prescaler 1, 2, 4, 8 0 2 T1CKPS<1:0> TMR1CS 1 SYNCC2OUT(2) Sleep input Synchronize det
RA4/AN3/T1G/OSC2/CLKOUT
INTOSC Without CLKOUT T1OSCEN
0 T1GSS
* ST Buffer is low power type when using LP OSC, or high-speed type when using T1CKI. Note 1: 2: Timer 1 increments on the rising edge. SYNCC2OUT is the synchronized output from comparator 2 (see Figure 9-2 on page 64).
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 49
PIC16F785
6.1 Timer1 Modes of Operation 6.3 Timer1 Prescaler
Timer1 can operate in one of three modes: * 16-bit Timer with prescaler * 16-bit Synchronous counter * 16-bit Asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. In Counter and Timer modules, the counter/timer clock can be gated by the Timer 1 gate, which can be selected as either the T1G pin or Comparator 2 output. If an external clock oscillator is needed (and the microcontroller is using the LP oscillator or INTOSC without CLKOUT), Timer1 can use the LP oscillator as a clock source. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. Timer1 has four prescaler options allowing 1, 2, 4, or 8 divisions of the clock input. The T1CKPS bits (T1CON<5:4>) control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
6.4
Timer1 Gate
Timer1 gate source is software configurable to be T1G pin or the output of Comparator 2. This allows the device to directly time external events using T1G or analog events using Comparator 2. See CM2CON1 (Register 9-3) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D Converter and many other applications. For more information on Delta-Sigma A/D Converters, see the Microchip web site (www.microchip.com). Note: TMR1GE bit (T1CON<6>) must be set to use either T1G or C2OUT as the Timer1 gate source. See Register 9-3 for more information on selecting the Timer1 gate source.
6.2
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1<0>) is set. To enable the interrupt on rollover, you must set these bits: * Timer1 interrupt Enable bit (PIE1<0>) * PEIE bit (INTCON<6>) * GIE bit (INTCON<7>) The interrupt is cleared by clearing the TMR1IF in the Interrupt Service Routine. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
Timer1 gate can be inverted using the T1GINV bit (T1CON<7>), whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active high or active low time between events.
FIGURE 6-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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Preliminary
2004 Microchip Technology Inc.
PIC16F785
REGISTER 6-1: T1CON -- TIMER1 CONTROL REGISTER (ADDRESS: 10h)
R/W-0 T1GINV bit 7 bit 7 T1GINV: Timer1 Gate Invert bit (1) 1 = Timer1 gate is high true (see bit 6) 0 = Timer1 gate is low true (see bit 6) TMR1GE: Timer1 Gate Enable bit (2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if Timer1 gate is true (see bit 7) 0 = Timer1 is on independent of Timer1 gate T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: LP Oscillator Enable Control bit If System Clock is INTOSC without CLKOUT or LP mode: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: 2: T1GINV bit inverts the Timer1 gate logic, regardless of source. TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by T1GSS bit (CM2CON1<1>), as a Timer1 gate source. R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0 TMR1GE T1CKPS1 T1CKPS0 T1OSCEN
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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Preliminary
DS41249A-page 51
PIC16F785
6.5 Timer1 Operation in Asynchronous Counter Mode 6.6 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated for 32.768 kHz. It will continue to run during Sleep. It is primarily intended for a 32.768 kHz tuning fork crystal. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is also the LP oscillator or is derived from the internal oscillator. As with the system LP oscillator, the user must provide a software time delay to ensure proper oscillator start-up. SLEEP mode will not disable the system clock when the system clock and Timer1 share the LP oscillator. TRISA<5> and TRISA<4> bits are set when the Timer1 oscillator is enabled. RA5 and RA4 read as `0' and TRISA<5> and TRISA<4> bits read as `1'. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer 1.
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 6.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: The ANSEL0 (91h) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
6.5.1
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Examples in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.
6.7
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To setup the timer to wake the device: * Timer1 must be on (T1CON<0>) * TMR1IE bit (PIE1<0>) must be set * PEIE bit (INTCON<6>) must be set The device will wake-up on an overflow. If the GIE bit (INTCON<7>) is set, the device will wake-up and jump to the Interrupt Service Routine (0004h) on an overflow. If the GIE bit is clear, execution will continue with the next instruction.
TABLE 6-1:
Addr
0Bh, 8Bh 0Ch 0Eh 0Fh 10h 1Ah 8Ch 91h Legend:
REGISTERS ASSOCIATED WITH TIMER1
Bit 7
GIE EEIF
Name
INTCON PIR1 TMR1L TMR1H T1CON
Bit 6
PEIE ADIF
Bit 5
T0IE CCP1IF
Bit 4
INTE C2IF
Bit 3
RAIE C1IF
Bit 2
T0IF OSFIF
Bit 1
INTF TMR2IF
Bit 0
RAIF TMR1IF
Value on: POR, BOR
0000 0000 0000 0000 xxxx xxxx xxxx xxxx
Value on all other Resets
0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 00-- --10 0000 0000 1111 1111
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register T1GINV TMR1GE T1CKPS1 -- CCP1IE ANS5 T1CKPS0 -- C2IE ANS4 T1OSCEN -- C1IE ANS3 T1SYNC -- OSFIE ANS2 TMR1CS T1GSS TMR2IE ANS1 TMR1ON C2SYNC TMR1IE ANS0
0000 0000 00-- --10 0000 0000 1111 1111
CM2CON1 MC1OUT MC2OUT PIE1 ANSEL0 EEIE ANS7 ADIE ANS6
x = unknown, u = unchanged, -- = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
DS41249A-page 52
Preliminary
2004 Microchip Technology Inc.
PIC16F785
7.0 TIMER2 MODULE
7.1 Timer2 Operation
The Timer2 module timer is an 8-bit timer with the following features: * * * * * 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16 by 1's) * Interrupt on TMR2 match with PR2 Timer2 has a control register shown in Register 7-1. TMR2 can be shut-off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 7-1 is a simplified block diagram of the Timer2 module. The prescaler and postscaler selection of Timer2 are controlled by this register. Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS<1:0> (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written.
REGISTER 7-1:
T2CON -- TIMER2 CONTROL REGISTER (ADDRESS: 12h)
U-0 -- bit 7 R/W-0 TOUTPS3 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 R/W-0 R/W-0 T2CKPS0 bit 0 TMR2ON T2CKPS1
bit 7 bit 6-3
Unimplemented: Read as `0' TOUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 2
bit 1-0
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 53
PIC16F785
7.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
TMR2 Output Sets Flag bit TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16 2 T2CKPS<1:0>
TMR2
Reset
Comparator EQ PR2
Postscaler 1:1 to 1:16 4 TOUTPS<3:0>
TABLE 7-1:
Addr 0Bh, 8Bh 0Ch 11h 12h 8Ch 92h Legend: Name INTCON PIR1 TMR2 T2CON PIE1 PR2
REGISTERS ASSOCIATED WITH TIMER2
Bit 7 GIE EEIF Bit 6 PEIE ADIF Bit 5 T0IE CCP1IF Bit 4 INTE C2IF Bit 3 RAIE C1IF Bit 2 T0IF OSFIF Bit 1 INTF TMR2IF Bit 0 RAIF TMR1IF Value on: POR, BOR 0000 0000 0000 0000 0000 0000 TOUTPS0 C1IE TMR2ON T2CKPS1 T2CKPS0 OSFIE TMR2IE TMR1IE -000 0000 0000 0000 1111 1111 Value on all other Resets 0000 0000 0000 0000 0000 0000 -000 0000 0000 0000 1111 1111
Holding register for the 8-bit TMR2 register -- EEIE TOUTPS3 TOUTPS2 ADIE CCP1IE TOUTPS1 C2IE
Timer2 Module Period register
x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module.
DS41249A-page 54
Preliminary
2004 Microchip Technology Inc.
PIC16F785
8.0 CAPTURE/COMPARE/PWM (CCP) MODULE
TABLE 8-1: CCP MODE - TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2 CCP Mode Capture Compare PWM
The Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: * 16-bit Capture register * 16-bit Compare register * PWM Master/Slave Duty Cycle register Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP. The special event trigger is generated by a compare match and will clear both TMR1H and TMR1L registers.
REGISTER 8-1:
CCP1CON -- CCP OPERATION REGISTER (ADDRESS: 15h)
U-0 -- bit 7 U-0 -- R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0
bit 7-6 bit 5-4
bit 3-0
Unimplemented: Read as `0'. DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. CCP1M<3:0>: CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; TMR1 is reset, and A/D conversion is started if the A/D module is enabled. CCP1 pin is unaffected.) 110x = PWM mode: CCP1 output is high true. 111x = PWM mode: CCP1 output is low true. Legend: R = Readable bit - n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 55
PIC16F785
8.1 Capture Mode
8.1.4 CCP PRESCALER
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC5/CCP1. An event is defined as one of the following and is configured by CCP1CON<3:0>: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge There are four prescaler settings specified by bits CCP1M<3:0> (CCP1CON<3:0>). Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
When a capture is made, the interrupt request flag bit CCP1IF (PIR1<5>) is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value.
EXAMPLE 8-1:
CLRF MOVLW
8.1.1
CCP1 PIN CONFIGURATION
CHANGING BETWEEN CAPTURE PRESCALERS
In Capture mode, the RC5/CCP1 pin should be configured as an input by setting the TRISC<5> bit. Note: If the RC5/CCP1 pin is configured as an output, a write to the port can cause a capture condition.
MOVWF
CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ;Load CCP1CON with this ; value
FIGURE 8-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF (PIR1<5>)
Prescaler / 1, 4, 16 RC5/CCP1 pin
CCPR1H and Edge Detect Capture Enable TMR1H CCP1CON<3:0> Q's
CCPR1L
TMR1L
8.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
8.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<5>) clear to avoid false interrupts and should clear the flag bit CCP1IF (PIR1<5>) following any such change in Operating mode.
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Preliminary
2004 Microchip Technology Inc.
PIC16F785
8.2 Compare Mode
8.2.1 CCP1 PIN CONFIGURATION
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC5/CCP1 pin is: * Driven high * Driven low * Remains unchanged The action on the pin is based on the value of control bits CCP1M<3:0> (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF (PIR1<5>) is set. The user must configure the RC5/CCP1 pin as an output by clearing the TRISC<5> bit. Note: Clearing the CCP1CON register will force the RC5/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch.
8.2.2
TIMER1 MODE SELECTION
FIGURE 8-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCP1CON<3:0> Mode Select Set Flag bit CCP1IF (PIR1<5>) 4 CCPR1H CCPR1L Q S R Output Logic Comparator TMR1H TMR1L
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
8.2.3
SOFTWARE INTERRUPT MODE
RC5/CCP1 Pin
When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the RC5/CCP1 pin is not affected. The CCP1IF (PIR1<5>) bit is set, causing a CCP interrupt (if enabled). See Register 8-1.
8.2.4
Match
SPECIAL EVENT TRIGGER
TRISC<5> Output Enable Special Event Trigger Special Event Trigger will:
In this mode (CCP1M<3:0> = 1011), an internal hardware trigger is generated, which may be used to initiate an action. See Register 8-1. The special event trigger output of CCP resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special event trigger output also starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP module will not set interrupt flag bit TMR1IF (PIR1<0>).
* clear TMR1H and TMR1L registers * NOT set interrupt flag bit TMR1F (PIR1<0>) * set the GO/DONE bit (ADCON0<1>)
TABLE 8-2:
Addr Name
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR1CS T1GSS TMR1ON C2SYNC 0000 0000 00-- --10 xxxx xxxx xxxx xxxx CCP1M3 TRISC3 C1IE CCP1M2 TRISC2 OSFIE CCP1M1 TRISC1 TMR2IE CCP1M0 TRISC0 TMR1IE --00 0000 --11 1111 0000 0000 Value on all other Resets 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 00-- --10 uuuu uuuu uuuu uuuu --00 0000 --11 1111 0000 0000
0Bh 8Bh 0Ch 0Eh 0Fh 10h 1Ah 13h 14h 15h 87h, 187h 8Ch
INTCON PIR1 TMR1L TMR1H T1CON CM2CON1 CCPR1L CCPR1H CCP1CON TRISC PIE1
GIE EEIF
PEIE ADIF
T0IE CCP1IF
INTE C2IF
RAIE C1IF
T0IF OSFIF
INTF TMR2IF
RAIF TMR1IF
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register T1GINV TMR1GE T1CKPS1 -- T1CKPS0 -- T1OSCEN -- T1SYNC --
MC1OUT MC2OUT
Capture/Compare/PWM Register1 Low Byte Capture/Compare/PWM Register1 High Byte -- TRISC7 EEIE -- TRISC6 ADIE DC1B1 TRISC5 CCP1IE DC1B0 TRISC4 C2IE
Legend:
-- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare or Timer1 module.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 57
PIC16F785
8.3 CCP PWM Mode
8.3.1 PWM PERIOD
In Pulse Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the RC5/CCP1 pin. Since the RC5/CCP1 pin is multiplexed with the PORTC data latch, the TRISC<5> must be cleared to make the RC5/CCP1 pin an output. Note: Clearing the CCP1CON register will force the PWM output latch to the default inactive levels. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the formula of Equation 8-1.
EQUATION 8-1:
PWM period = [ ( PR2 ) + 1 ] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The RC5/CCP1 pin is set. (exception: if PWM duty cycle = 0%, the pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 7.1 "Timer2 Operation") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
Figure 8-3 shows a simplified block diagram of PWM operation. For a step by step procedure on how to set up the CCP module for PWM operation, see Section 8.3.5 "Setup for PWM Operation".
FIGURE 8-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
CCPR1H (Slave) RC5/CCP1 Comparator
(1)
8.3.2
PWM DUTY CYCLE
R S
Q
TMR2
TRISC<5> Comparator Clear Timer2, toggle PWM pin and latch duty cycle
PR2
The PWM duty cycle is specified by writing to the CCPR1L register and to the DC1B<1:0> (CCP1CON<5:4>) bits. Up to 10 bits of resolution is available. The CCPR1L contains the eight MSbs and the DC1B<1:0> contains the two LSbs. CCPR1L and DC1B<1:0> can be written to at any time. In PWM mode, CCPR1H is a read-only register. This 10-bit value is represented by CCPR1L (CCP1CON<5:4>). Equation 8-2 is used to calculate the PWM duty cycle in time.
Note 1:
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
EQUATION 8-2:
PWM duty cycle = ( CCPR1L:CCP1CON<5:4> ) * TOSC * (TMR2 prescale value)
The PWM output (Figure 8-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 8-4:
PERIOD DUTY CYCLE
CCP PWM OUTPUT
TMR2 = PR2 TMR2 = DUTY CYCLE
TMR2 = 0
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Preliminary
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PIC16F785
CCPR1L and DC1B<1:0> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e. the period is complete). In PWM mode, CCPR1H is a read only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. Because of the buffering, the module waits until the timer resets, instead of starting immediately. This means that enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle (4 TOSC). When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the RC5/CCP1 pin is cleared. The maximum PWM resolution is a function of PR2 as shown by Equation 8-3.
EQUATION 8-3:
log [ 4 ( PR2 + 1 ) ] Resolution = ----------------------------------------- bits log ( 2 )
Note:
If the PWM duty cycle value is longer than the PWM period, the assigned PWM pin(s) will remain unchanged.
TABLE 8-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
1.22 kHz(1) 16 0xFF 10 4.88 kHz(1) 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 6.6
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
Note 1: Changing duty cycle will cause a glitch.
8.3.3
OPERATION IN SLEEP MODE
8.3.5
SETUP FOR PWM OPERATION
In Sleep mode, all clock sources are disabled. Timer2 will not increment, and the state of the module will not change. If the RC5/CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state.
The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. Configure the PWM pin (RC5/CCP1) as an input by setting the TRISC<5> bit. Set the PWM period by loading the PR2 register. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values. Set the PWM duty cycle by loading the CCPR1L register and CCP1CON<5:4> bits. Configure and start TMR2: * Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). * Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). * Enable Timer2 by setting the TMR2ON bit (T2CON<2>). Enable PWM output after a new PWM cycle has started: * Wait until TMR2 overflows (TMR2IF bit is set). * Enable the RC5/CCP1 pin output by clearing the TRISC<5> bit.
8.3.3.1
OPERATION WITH FAIL-SAFE CLOCK MONITOR
If the Fail-Safe Clock Monitor is enabled, a clock failure will force the CCP to be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. See Section 3.0 "Clock Sources" for additional details.
4. 5.
8.3.4
EFFECTS OF A RESET
Any Reset will force all ports to Input mode and the CCP registers to their Reset states.
6.
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TABLE 8-4:
Addr
0Bh, 8Bh 0Ch 11h 12h 13h 14h 15h 87h 8Ch 92h
REGISTERS ASSOCIATED WITH CCP AND TIMER2
Bit 7
GIE EEIF
Name
INTCON PIR1 TMR2 T2CON CCPR1L CCPR1H CCP1CON TRISC PIE1 PR2
Bit 6
PEIE ADIF
Bit 5
T0IE CCP1IF
Bit 4
INTE C2IF
Bit 3
RAIE C1IF
Bit 2
T0IF OSFIF
Bit 1
INTF TMR2IF
Bit 0
RAIF TMR1IF
Value on: POR, BOR
0000 0000 0000 0000 0000 0000
Value on all other Resets
0000 0000 0000 0000 0000 0000 -000 0000 uuuu uuuu uuuu uuuu 0000 0000 --11 1111 0000 0000 1111 1111
Timer2 Module register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 xxxx xxxx xxxx xxxx
Capture/Compare/PWM Register1 Low Byte Capture/Compare/PWM Register1 High Byte -- TRISC7 EEIE -- TRISC6 ADIE DC1B1 TRISC5 CCP1IE DC1B0 TRISC4 C2IE CCP1M3 TRISC3 C1IE CCP1M2 TRISC2 OSFIE CCP1M1 TRISC1 TMR2IE CCP1M0 TRISC0 TMR1IE
0000 0000 --11 1111 0000 0000 1111 1111
Timer2 Module Period register
Legend:
-- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the CCP or Timer2 modules.
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9.0 COMPARATOR MODULE
A complete table showing the output state versus input conditions and the polarity bit is shown in Table 9-1. The comparator module has two separate voltage comparators: Comparator C1 and Comparator C2. Each comparator offers the following list of features: * * * * * * * * * * Control and configuration register Comparator output available externally Programmable output polarity Interrupt-on-change flags Wake-up from SLEEP Configurable as feedback input to the PWM Programmable four input multiplexer Programmable two input reference selections Programmable speed/power Output synchronization to Timer1 clock input (Comparator C2 only)
TABLE 9-1:
C1OUTPUT STATE VERSUS INPUT CONDITIONS
C1POL 0 0 1 1 C1OUT 0 1 1 0
Input Condition C1VN > C1VP C1VN < C1VP C1VN > C1VP C1VN < C1VP
Note 1: The internal output of the comparator is latched at the end of each instruction cycle. External outputs are not latched. 2: The C1 interrupt will operate correctly with C1OE set or cleared. 3: To output C1 on RA2/AN2/T0CKI/INT/C1OUT: (C1OE=1) & (C1ON=1) & (TRISA<2>=0). C1SP (CM1CON0<3>) configures the speed of the comparator. When C1SP is set, the comparator operates at its normal speed. Clearing C1SP operates the comparator in a slower, low-power mode.
9.1
Control Registers
Both comparators have separate control and configuration registers: CM1CON0 for C1 and CM2CON0 for C2. In addition, Comparator C2 has a second control register, CM2CON1, for synchronization control and simultaneous reading of both comparator outputs.
9.1.1
COMPARATOR C1 CONTROL REGISTER
The CM1CON0 register (shown in Register 9-1) contains the control and Status bits for the following: * * * * * Comparator enable Comparator input selection Comparator reference selection Output mode Comparator speed
Setting C1ON (CM1CON0<7>) enables Comparator C1 for operation. Bits C1CH<1:0> (CM1CON0<1:0>) select the comparator input from the four analog pins AN<7:5,1>. Note: To use AN<7:5,1> as analog inputs the appropriate bits must be programmed to `1' in the ANSEL0 register.
Setting C1R (CM1CON0<2>) selects the C1VREF output of the comparator voltage reference module as the reference voltage for the comparator. Clearing C1R selects the C1IN+ input on the RA0/AN0/C1IN+/ICSPDAT pin. The output of the comparator is available internally via the C1OUT flag (CM1CON0<6>). To make the output available for an external connection, the C1OE bit (CM1CON0<5>) must be set. The polarity of the comparator output can be inverted by setting the C1POL bit (CM1CON0<4>). Clearing C1POL results in a non-inverted output.
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FIGURE 9-1: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
C1CH<1:0> 2 D RA1/AN1/C12IN0-/VREF/ICSPCLK RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 RC3/AN7/C12IN3-/OP1 0 1 MUX 2 3 C1ON(1) C1R C1VN RA0/AN0/C1IN+/ICSPDAT C1VREF 0 MUX 1 C1VP C1 C1POL Note 1: When C1ON = 0, the C1 comparator will produce a `0' output to the XOR Gate. C1OUT RA2/AN2/T0CKI/INT/C1OUT C1SP Q1 EN Q C1POL To Data Bus RD_CM1CON0 Set C1IF D Q3*RD_CM1CON0 Q To PWM Logic EN CL NRESET
C1OE
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REGISTER 9-1: COMPARATOR C1 CONTROL REGISTER 0 (CM1CON0: 119h)
R/W-0 C1ON bit 7 bit 7 C1ON: Comparator C1 Enable bit 1 = C1 Comparator is enabled 0 = C1 Comparator is disabled C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 1, C1VP < C1VN C1OUT = 0, C1VP > C1VN If C1POL = 0 (non-inverted polarity): C1OUT = 1, C1VP > C1VN C1OUT = 0, C1VP < C1VN C1OE: Comparator C1 Output Enable bit 1 = C1OUT is present on the RA2/AN2/T0CKI/INT/C1OUT pin(1) 0 = C1OUT is internal only C1POL: Comparator C1 Output Polarity Select bit 1 = C1OUT logic is inverted 0 = C1OUT logic is not inverted C1SP: Comparator C1 Speed Select bit 1 = C1 operates in normal speed mode 0 = C1 operates in low-power, slow speed mode C1R: Comparator C1 Reference Select bit (non-inverting input) 1 = C1VP connects to C1VREF output 0 = C1VP connects to RA0/AN0/C1IN+/ICSPDAT C1CH<1:0>: Comparator C1 Channel Select bit 00 = C1VN of C1 connects to RA1/AN1/C12IN0-/VREF/ICSPCLK 01 = C1VN of C1 connects to RC1/AN5/C12IN1-/PH1 10 = C1VN of C1 connects to RC2/AN6/C12IN2-/OP2 11 = C1VN of C1 connects to RC3/AN7/C12IN3-/OP1 Note 1: C1OUT will only drive RA2/AN2/T0CKI/INT/C1OUT if: (C2OE = 1) & (C2ON = 1) & (TRISA<2> = 0) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 C1OUT R/W-0 C1OE R/W-0 C1POL R/W-0 C1SP R/W-0 C1R R/W-0 C1CH1 R/W-0 C1CH0 bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
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9.1.2 COMPARATOR C2 CONTROL REGISTERS
The comparator output, C2OUT, can be inverted by setting the C2POL bit (CM2CON0<4>). Clearing C2POL results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 9-2.
The CM2CON0 register is a functional copy of the CM1CON0 register described in Section 9.1.1. A second control register, CM2CON1, is also present for control of an additional synchronizing feature, as well as mirrors of both comparator outputs.
TABLE 9-2:
9.1.2.1
Control Register CM2CON0
C2VN > C2VP C2VN < C2VP C2VN > C2VP C2VN < C2VP
C2 OUTPUT STATE VERSUS INPUT CONDITIONS
C2POL 0 0 1 1 C2OUT 0 1 1 0
The CM2CON0 register, shown in Register 9-2, contains the control and Status bits for Comparator C2. Setting C2ON (CM2CON0<7>) enables Comparator C2 for operation. Bits C2CH<1:0> (CM2CON0<1:0>) select the comparator input from the four analog pins, AN<7:5,1>. Note 1: To use AN<7:5,1> as analog inputs, the appropriate bits must be programmed to 1 in the ANSEL0 register. C2R (CM2CON0<2>) selects the reference to be used with the comparator. Setting C2R (CM2CON0<2>) selects the C2VREF output of the comparator voltage reference module as the reference voltage for the comparator. Clearing C2R selects the C2IN+ input on the RC0/AN4/C2IN+ pin. The output of the comparator is available internally via the C2OUT bit (CM2CON0<6>). To make the output available for an external connection, the C2OE bit (CM2CON0<5>) must be set.
Input Condition
Note 1: The internal output of the comparator is latched at the end of each instruction cycle. External outputs are not latched. 2: The C2 interrupt will operate correctly with C2OE set or cleared. An external output is not required for the C2 interrupt. 3: For C2 output on RC4/C2OUT/PH2: (C2OE=1) & (C2ON=1) & (TRISA<4>=0). C2SP (CM2CON0<3>) configures the speed of the comparator. When C2SP is set, the comparator operates at its normal speed. Clearing C2SP operates the comparator in low-power mode.
FIGURE 9-2:
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C2POL D Q1 C2CH<1:0> 2 D C2ON(1) C2SP Q3*RD_CM2CON0 Q EN Q To Data Bus RD_CM2CON0 Set C2IF EN CL NRESET C2OUT C2SYNC C2POL D Q 0 MUX 1 To PWM Logic
RA1/AN1/C12IN0-/VREF/ICSPCLK RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 RC3/AN7/C12IN3-/OP1
0
1 MUX C2VN C2 2 C2VP 3
C20E
C2R RC0/AN4/C2IN+ C2VREF 0 MUX 1
RC4/C2OUT/PH2 SYNCC2OUT(2)
From TMR1 Clock
Note 1: When C2ON = 0, the C2 comparator will produce a `0' output to the XOR Gate. 2: Timer1 gate control (see Figure 6-2 on page 50).
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REGISTER 9-2: COMPARATOR C2 CONTROL REGISTER 0 (CM2CON0: 11AH)
R/W-0 C2ON bit 7 bit 7 C2ON: Comparator C2 Enable bit 1 = C2 Comparator is enabled 0 = C2 Comparator is disabled C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 1, C2VP < C2VN C2OUT = 0, C2VP > C2VN If C2POL = 0 (non-inverted polarity): C2OUT = 1, C2VP > C2VN C2OUT = 0, C2VP < C2VN C2OE: Comparator C2 Output Enable bit 1 = C2OUT is present on RC4/C2OUT/PH2(1) 0 = C2OUT is internal only C2POL: Comparator C2 Output Polarity Select bit 1 = C2OUT logic is inverted 0 = C2OUT logic is not inverted C2SP: Comparator C2 Speed Select bit 1 = C2 operates in normal speed mode 0 = C2 operates in low power, slow speed mode. C2R: Comparator C2 Reference Select bits (non-inverting input) 1 = C2VP connects to C2VREF 0 = C2VP connects to RC0/AN4/C2IN+ C2CH<1:0>: Comparator C2 Channel Select bits 00 = C2VN of C2 connects to RA1/AN1/C12IN0-/VREF/ICSPCLK 01 = C2VN of C2 connects to RC1/AN5/C12IN1-/PH1 10 = C2VN of C2 connects to RC2/AN6/C12IN2-/OP2 11 = C2VN of C2 connects to RC3/AN7/C12IN3-/OP1 Note 1: C2OUT will only drive RC4/C2OUT/PH2 if: (C2OE = 1) & (C2ON = 1) & (TRISC<4> = 0) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 C2OUT R/W-0 C2OE R/W-0 C2POL R/W-0 C2SP R/W-0 C2R R/W-0 C2CH1 R/W-0 C2CH0 bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
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9.1.2.2 Control Register CM2CON1
Comparator C2 has one additional feature: its output can be synchronized to the Timer1 clock input. Setting C2SYNC (CM2CON1<0>) synchronizes the output of Comparator 2 to the falling edge of Timer 1's clock input (see Figure 9-2 and Register 9-3). The CM2CON1 register also contains mirror copies of both comparator outputs, MC1OUT and MC2OUT (CM2CON1<7:6>). The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers.
Note 1: Obtaining the status of C1OUT or C2OUT by reading CM1CON1 does not affect the comparator interrupt mismatch registers.
REGISTER 9-3:
COMPARATOR C2 CONTROL REGISTER 1 (CM2CON1: 11Bh)
R-0 bit 7 R-0 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 T1GSS R/W-0 C2SYNC bit 0 MC1OUT MC2OUT
bit 7 bit 6 bit 5-2 bit 1
MC1OUT: Mirror Copy of C1OUT (CM1CON0<6>) MC2OUT: Mirror Copy of C2OUT (CM2CON0<6>) Unimplemented: Read as `0' T1GSS: Timer1 Gate Source Select bit 1 = Timer1 gate source is RA4/AN3/T1G/OSC2/CLKOUT 0 = Timer1 gate source is SYNCC2OUT. C2SYNC: C2 Output Synchronous Mode bit 1 = C2 output is synchronous to falling edge of TMR1 clock 0 = C2 output is asynchronous Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 0
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9.2 Comparator Outputs 9.3 Comparator Interrupts
The comparator outputs are read through the CM1CON0, COM2CON0 or CM2CON1 registers. CM1CON0 and CM2CON0 each contain the individual comparator output of comparator 1 and comparator 2, respectively. CM2CON2 contains a mirror copy of both comparator outputs facilitating a simultaneous read of both comparators. These bits are read-only. The comparator outputs may also be directly output to the RA2/AN2/T0CKI/INT/C1OUT and RC4/C2OUT/PH2 I/O pins. When enabled, multiplexers in the output path of the RA2 and RC4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 9-1 and Figure 9-2 show the output block diagrams for Comparators 1 and 2, respectively. The TRIS bits will still function as an output enable/disable for the RA2/AN2/T0CKI/INT/C1OUT and RC4/C2OUT/PH2 pins while in this mode. The polarity of the comparator outputs can be changed using the C1POL and C2POL bits (CMxCON0<4>). Timer1 gate source can be configured to use the T1G pin or Comparator 2 output as selected by the T1GSS bit (CM2CON1<1>). The Timer1 gate feature can be used to time the duration or interval of analog events. The output of Comparator 2 can also be synchronized with Timer1 by setting the C2SYNC bit (CM2CON1<0>). When enabled, the output of Comparator 2 is latched on the falling edge of Timer1 clock source. If a prescaler is used with Timer1, Comparator 2 is latched after the prescaler. To prevent a race condition, the Comparator 2 output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator 2 Block Diagram (Figure 9-2) and the Timer1 Block Diagram (Figure 6-1) for more information. It is recommended to synchronize Comparator 2 with Timer1 by setting the C2SYNC bit when Comparator 2 is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if Comparator 2 changes during an increment. The comparator interrupt flags are set whenever there is a change in the output value of its respective comparator. Software will need to maintain information about the status of the output bits, as read from CM2CON0<7:6>, to determine the actual change that has occurred. The CxIF bits, PIR1<4:3>, are the Comparator Interrupt Flags. Each comparator interrupt bit must be reset in software by clearing it to `0'. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. The CxIE bits (PIE1<4:3>) and the PEIE bit (INTCON<6>) must be set to enable the interrupts. In addition, the GIE bit must also be set. If any of these bits are cleared, the interrupt is not enabled, though the CxIF bits will still be set if an interrupt condition occurs. The comparator interrupt of the PIC16F785 differs from previous designs in that the interrupt flag is set by the mismatch edge and not the mismatch level. This means that the interrupt flag can be reset without the additional step of reading or writing the CMxCON0 register to clear the mismatch registers. When the mismatch registers are not cleared, an interrupt will not occur when the comparator output returns to the previous state. When the mismatch registers are cleared, an interrupt will occur when the comparator returns to the previous state. Note 1: If a change in the CMxCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF (PIR1<4:3>) interrupt flag may not get set. 2: When either comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts.
9.4
Effects of RESET
A RESET forces all registers to their RESET state. This disables both comparators.
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NOTES:
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10.0 VOLTAGE REFERENCES
10.1.2
There are two voltage references available in the PIC16F785: The voltage referred to as the comparator reference (CVREF) is a variable voltage based on VDD; The voltage referred to as the VR reference (VR) is a fixed voltage derived from a stable bandgap source. Each source may be individually routed internally to the comparators or output, buffered or unbuffered, on the RA1/AN1/C12IN0-/VREF/ICSPCLK pin.
VOLTAGE REFERENCE ACCURACY/ERROR
10.1
Comparator Reference
The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The VRCON register (Register 10-1) controls the voltage reference module shown in Figure 10-1.
The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 10-1) keep CVREF from approaching VSS or VDD. The exception is when the module is disabled by clearing all CVROE, C1VREN and C2VREN bits. When disabled, the reference voltage is VSS when VR<3:0> is `0000' and the VRR (VRCON<5>) bit is set. This allows the comparators to detect a zerocrossing and not consume CVREF module current. The voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the comparator voltage reference can be found in Table 18-8.
10.1.1
CONFIGURING THE VOLTAGE REFERENCE
The voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range. The following equation determines the output voltages:
EQUATION 10-1:
VRR = 1 (low range): CVREF = VR<3:0> X VDD/24 VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0> X VDD/32)
FIGURE 10-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages 8R R R R R
VDD 8R CVREN(1) CVREF 16-1 Analog MUX VRR
15
* * *
0
VR3:VR0 C1VREN
CVROE
C1VREF to Comparator 1 Input
1 0
C2VREN
C2VREF to Comparator 2 Input
1 0 VR 1.2 V
Note 1: See Register 10-1, Bits 3-0.
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REGISTER 10-1: VOLTAGE REFERENCE CONTROL REGISTER (VRCON: 99H)
R/W-0 C1VREN bit 7 bit 7: R/W-0 C2VREN R/W-0 VRR U-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
C1VREN: Comparator 1 Voltage Reference Enable bit(1) 1 = CVREF circuit powered on and routed to C1VREF input of comparator 1 0 = 1.2 Volt VR routed to C1VREF input of comparator 1 C2VREN: Comparator 2 Voltage Reference Enable bit(1) 1 = CVREF circuit powered on and routed to C2VREF input of comparator 2 0 = 1.2 Volt VR routed to C2VREF input of comparator 2 VRR: Comparator Voltage Reference CVREF Range Selection bit 1 = Low Range 0 = High Range Unimplemented: Read as `0' VR<3:0>: Comparator Voltage Reference CVREF Value Selection 0 VR<3:0> 15 When VRR = 1 & CVREN = 1: CVREF = (VR<3:0> x VDD / 24) When VRR = 0 & CVREN = 1: CVREF = (VDD / 4) + (VR<3:0> x VDD / 32) When CxVREN = 0: CxVREF = 1.2 volts from VR module Note 1: When C1VREN, C2VREN and CVROE (Register 10-2) are all low, the CVREF circuit is powered down and does not contribute to IDD current. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = bit is cleared x = bit is unknown
bit 6:
bit 5:
bit 4: bit 3-0:
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PIC16F785
10.2 VR REFERENCE MODULE
The VR Reference Module generates a 1.2V nominal output voltage for use by the ADC and comparators. The output voltage can also be brought out to the VREF pin for user applications. This module uses a Bandgap as a reference. See Table 18-9 for detailed specifications. Register 10-2 shows the control register for the VR module.
REGISTER 10-2:
VOLTAGE REFERENCE CONTROL REGISTER (REFCON: 98h)
U-0 -- bit7 U-0 -- R-0 BGST R/W-0 VRBB R/W-0 VREN R/W-0 VROE R/W-0 CVROE U-0 -- bit0
bit 7-6: bit 5:
Unimplemented: Read as `0' BGST: Bandgap Reference Voltage Stable Flag bit 1 = Reference is stable 0 = Reference is not stable VRBB: Voltage Reference Buffer Bypass bit 1 = VREF output is not buffered 0 = VREF output is buffered VREN: Voltage Reference Enable bit (VR = 1.2V nominal) 1 = VR reference is enabled 0 = VR reference is disabled and does not consume any current VROE: Voltage Reference Output Enable bit If CVROE = 0: 1 = VREF output on RA1/AN1/C12IN0-/VREF/ICSPCLK pin is 1.2 volt VR analog reference 0 = Disabled, 1.2 volt VR analog reference is used internally only If CVROE = 1: VROE has no effect. CVROE: Comparator Voltage Reference Output Enable bit (see Figure 10-2) 1 = VREF output on RA1/AN1/C12IN0-/VREF/ICSPCLK pin is CVREF voltage 0 = VREF output on RA1/AN1/C12IN0-/VREF/ICSPCLK pin is controlled by VROE Unimplemented: Read as `0'
bit 4:
bit 3:
bit 2:
bit 1
bit 0:
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' - bit as set
U = Unimplemented bit, read as `0' `0' = bit is cleared x = bit is unknown
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10.2.1 VR STABILIZATION PERIOD
When the voltage reference module is enabled, it will require some time for the reference and its amplifier circuits to stabilize. The user program must include a small delay routine to allow the module to settle. See the electrical specifications section for the minimum delay requirement. The internal circuitry automatically recognizes when the voltage reference is required by the combination and purpose of various SFR control bits. The VREN enable bit allows the user to keep the voltage reference enabled even when SFR control bits would otherwise disable the reference. This precludes the need to wait for the voltage reference to stabilize when modules are switched in and out of service.
FIGURE 10-2:
VR REFERENCE BLOCK DIAGRAM
VREN
CVREF
CVROE
VRBB (CVROE + (VREN*VROE))
EN
1
1
Voltage Reference RDY VR BGST
VROUT
0
1X Analog Buffer
RA1/AN1/C12IN0-/VREF
0
To CVREF mux
TABLE 10-1:
REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES
Bit 7 C1ON C2ON -- TRISC7 -- RC7 ANS7 EEIF EEIE -- Bit 6 C1OUT C2OUT --
TRISC6
Address 119h 11Ah 11Bh 85h, 185h 87h, 187h 05h, 105h 07h, 107h 91h 0Ch 8Ch 98h 99h
Name CM1CON0 CM2CON0 TRISA TRISC PORTA PORTC ANSEL0 PIR1 PIE1 REFCON VRCON
Bit 5 C1OE C2OE --
TRISA5 TRISC5
Bit 4
Bit 3
Bit 2 C1R C2R --
Bit 1 C1CH1 C2CH1 TIGSS
TRISA1 TRISC1
Bit 0 C1CH0 C2CH0 C2SYNC
TRISA0 TRISC0
Value on: POR, BOR 0000 0000 0000 0000 00-- --10 --11 1111 1111 1111 --xx xxxx xxxx xxxx 1111 1111 0000 ---0 0000 ---0 --00 000000- 0000
Value on all other RESETS 0000 0000 0000 0000 00-- --10 --11 1111 1111 1111 --uu uuuu uuuu uuuu 1111 1111 0000 ---0 0000 ---0 --00 000000- 0000
C1POL C1SP C2POL C2SP -- --
CM2CON1 MC1OUT MC2OUT
TRISA4 TRISA3 TRISA2 TRISC4 TRISC3 TRISC2
-- RC6 ANS6 ADIF ADIE --
RA5 RC5 ANS5 CCP1IF CCP1IE BGST VRR
RA4 RC4 ANS4 C2IF C2IE VRBB --
RA3 RC3 ANS3 C1IF C1IE VREN VR3
RA2 RC2 ANS2
RA1 RC1 ANS1
RA0 RC0 ANS0 TMR1IF TMR1IE -- VR0
OSFIF TMR2IF OSFIE TMR2IE VROE CVROE VR2 VR1
C1VREN C2VREN
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used for comparator.
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11.0 OPERATIONAL AMPLIFIER (OPA) MODULE
11.2 OPAxCON Register
The OPA module is enabled by setting the OPAON bit (OPAxCON<7>). When enabled, OPAON forces the output driver of RC3/AN7/C12IN3-/OP1 for OPA1, and RC2/AN6/C12IN2-/OP2 for OPA2, into tri-state to prevent contention between the driver and the OPA output.
The OPA module has the following features: * Two independent Operational Amplifiers * External connections to all ports * 3 MHz Gain Bandwidth Product (GBWP)
11.1
Control Registers
Note:
The OPA1CON register, shown in Register 11-1, controls OPA1. OPA2CON, shown in Register 11-2, controls OPA2.
When OPA1 or OPA2 is enabled, the RC3/AN7/C12IN3-/OP1 pin, or RC2/AN6/C12IN2-/OP2 pin respectively, is driven by the op amp output, not by the PORTC driver. Refer to the Electrical specifications for the op amp output drive capability.
FIGURE 11-1:
OPA MODULE BLOCK DIAGRAM
OPA1CON RC7/AN9/OP1+ OPA1 RC6/AN8/OP1RC3/AN7/C12IN3-/OP1
TO ADC and Comparator MUXs
OPA2CON RB5/AN11/OP2+ OPA2 RB4/AN10/OP2RC2/AN6/C12IN2-/OP2
TO ADC and Comparator MUXs
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REGISTER 11-1: OP AMP 1 CONTROL REGISTER (OPA1CON: 11Ch)
R/W-0 OPAON bit 7 bit 7 OPAON: Op Amp Enable bit 1 = Op Amp1 is enabled 0 = Op Amp1 is disabled Unimplemented: Read as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 6-0
REGISTER 11-2:
OP AMP 2 CONTROL REGISTER (OPA2CON: 11Dh)
R/W-0 OPAON bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7
OPAON: Op Amp Enable bit 1 = Op Amp2 is enabled 0 = Op Amp2 is disabled Unimplemented: Read as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-0
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11.3 Effects of RESET
A device RESET forces all registers to their RESET state. This disables both op amps. Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To minimize the effect of leakage currents, the effective impedances connected to the OPA+ and OPA- inputs should be kept as small as possible and equal. Input offset voltage is a measure of the voltage difference between the OPA+ and OPA- inputs in a closed loop circuit with the OPA in its linear region. The offset voltage will appear as a DC offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. The input offset voltage is also affected by the common mode voltage. Open loop gain is the ratio of the output voltage to the differential input voltage, (OPA+) - (OPA-). The gain is greatest at DC and falls off with frequency. Gain Bandwidth Product or GBWP is the frequency at which the open loop gain falls off to 0 dB.
11.4
OPA Module Performance
Common AC and DC performance specifications for the OPA module: * * * * * Common Mode Voltage Range Leakage Current Input Offset Voltage Open Loop Gain Gain Bandwidth Product (GBWP)
Common mode voltage range is the specified voltage range for the OPA+ and OPA- inputs, for which the OPA module will perform to within its specifications. The OPA module is designed to operate with input voltages between 0 and VDD-1.4V. Behavior for common mode voltages greater than VDD-1.4V, or below 0V, are beyond the normal operating range.
TABLE 11-1:
Address 11Ch 11Dh 91h 93h 86h, 186h 87h, 187h
REGISTERS ASSOCIATED WITH THE OPA MODULE
Bit 7 Bit 6 -- -- ANS6 -- Bit 5 -- -- ANS5 -- Bit 4 -- -- ANS4 -- Bit 3 -- -- ANS3 Bit 2 -- -- ANS2 Bit 1 -- -- ANS1 Bit 0 -- -- Value on: POR, BOR Value on all other RESETS
Name
OPA1CON OPAON OPA2CON OPAON ANSEL0 ANSEL1 TRISB TRISC ANS7 --
0--- ---- 0--- ---0--- ---- 0--- ----
ANS0 1111 1111 1111 1111 ANS8 ---- 1111 ---- 1111
-- 1111 ---1111 ----
ANS11 ANS10 ANS9
-- -- --
TRISB7 TRISB6 TRISB5 TRISB4
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used for the OPA module.
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NOTES:
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12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by the VREF pin. Figure 12-1 shows the block diagram of the A/D on the PIC16F785.
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC16F785 has twelve analog I/O inputs, plus two internal inputs, multiplexed into one sample and hold circuit. The output of the sample and
FIGURE 12-1:
A/D BLOCK DIAGRAM
VDD VCFG = 0 VREF VCFG = 1
RA0/AN0/C1IN+/ICSPDAT RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA4/AN3/T1G/OSC2/CLKOUT RC0/AN4/C2IN+ RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 RC3/AN7/C12IN3-/OP1 RC6/AN8/OP1RC7/AN9/OP1+ RB4/AN10/OP2RB5/AN11/OP2+ CVREF VR
0
A/D GO/DONE ADFM ADON(1) ADRESH 13 Note 1: CHS<3:0> VSS When ADON = `0' all input channels are disconnected from ADC (no loading). 10 ADRESL 10
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12.1 A/D Configuration and Operation
12.1.3 VOLTAGE REFERENCE
There are four registers available to control the functionality of the A/D module: 1. 2. 3. 4. ANSEL0 (Register 12-1) ANSEL1 (Register 12-2) ADCON0 (Register 12-3) ADCON1 (Register 12-4) There are two options for the voltage reference to the A/D converter: either VDD is used or an analog voltage applied to VREF is used. The VCFG bit (ADCON0<6>) controls the voltage reference selection. If VCFG is set, then the voltage on the VREF pin is the reference; otherwise, VDD is the reference.
12.1.4
CONVERSION CLOCK
12.1.1
ANALOG PORT PINS
The ANS<11:0> bits (ANSEL1<3:0> and ANSEL0<7:0>) and the TRISA<4,2:0>, TRISB<5:4> and TRISC<7:6,3:0>> bits control the operation of the A/D port pins. Set the corresponding TRISx bits to `1' to set the pin output driver to its high-impedance state. Likewise, set the corresponding ANSx bit to disable the digital input buffer. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
The A/D conversion cycle requires 11 TAD. The source of the conversion clock is software selectable via the ADCS bits (ADCON1<6:4>). There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator)
12.1.2
CHANNEL SELECTION
There are fourteen analog channels on the PIC16F785. The CHS<3:0> bits (ADCON0<5:2>) control which channel is connected to the sample and hold circuit.
For correct conversion, the A/D conversion clock (1/TAD) must be selected to ensure a minimum TAD of 1.6 s. Table 12-1 shows a few TAD calculations for selected frequencies.
TABLE 12-1:
TAD VS. DEVICE OPERATING FREQUENCIES
Device Frequency
A/D Clock Source (TAD)
Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz (2) (2) (2) 000 100 ns 400 ns 500 ns 1.6 s 2 TOSC 4 TOSC 100 200 ns(2) 800 ns(2) 1.0 s(2) 3.2 s 8 TOSC 001 400 ns(2) 1.6 s 2.0 s 6.4 s 16 TOSC 101 800 ns(2) 3.2 s 4.0 s 12.8 s(3) 32 TOSC 010 1.6 s 6.4 s 8.0 s(3) 25.6 s(3) (3) (3) 64 TOSC 110 3.2 s 12.8 s 16.0 s 51.2 s(3) (1,4) (1,4) (1,4) A/D RC x11 2-6 s 2-6 s 2-6 s 2-6 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be performed during Sleep.
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12.1.5 STARTING A CONVERSION
The A/D conversion is initiated by setting the GO/DONE bit (ADCON0<1>). When the conversion is complete, the A/D module: * Clears the GO/DONE bit * Sets the ADIF flag (PIR1<6>) * Generates an interrupt (if enabled) If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion sample. Instead, the ADRESH:ADRESL registers will retain the value of the previous conversion. After an aborted conversion, a 2 TAD delay is required before another acquisition can be initiated. Following the delay, an input acquisition is automatically started on the selected channel. Note: The GO/DONE bit should not be set in the same instruction that turns on the A/D.
FIGURE 12-2:
A/D CONVERSION TAD CYCLES
TAD2 b9 Conversion Starts TAD3 b8 TAD4 b7 TAD5 b6 TAD6 b5 TAD7 b4 TAD8 b3 TAD9 TAD10 TAD11 b2 b1 b0
TCY to TAD TAD1
Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO bit
ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input
12.1.6
CONVERSION OUTPUT
The A/D conversion can be supplied in two formats: left or right justified. The ADFM bit (ADCON0<7>) controls the output format. Figure 12-3 shows the output formats.
FIGURE 12-3:
10-BIT A/D RESULT FORMAT
ADRESH ADRESL LSB bit 0 bit 7 bit 0
(ADFM = 0)
MSB bit 7
10-bit A/D Result (ADFM = 1) bit 7 MSB bit 0 bit 7
Unimplemented: Read as `0' LSB bit 0
Unimplemented: Read as `0'
10-bit A/D Result
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REGISTER 12-1: ANSEL0 -- ANALOG SELECT REGISTER (ADDRESS: 91h)
R/W-1 ANS7 bit 7 bit 7-0: ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input.(1) 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Port reads of pins configured assigned as analog inputs will read as `0'. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 ANS6 R/W-1 ANS5 R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0
REGISTER 12-2:
ANSEL1 -- ANALOG SELECT REGISTER (ADDRESS: 93h)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/W-1 ANS11 R/W-1 ANS10 R/W-1 ANS9 R/W-1 ANS8 bit 0
bit 7-0:
ANS<11:8>: Analog Select bits Analog select between analog or digital function on pins AN<11:8>, respectively. 1 = Analog input. Pin is assigned as analog input.(1) 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Port reads of pins assigned as analog inputs will read as `0'. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TABLE 12-2:
Analog Select Analog Channel I/O Pin
ANALOG SELECT CROSS REFERENCE
ANS10 AN10 RB4 ANS9 AN9 RC7 ANS8 AN8 RC6 ANS7 AN7 RC3 ANS6 AN6 RC2 ANS5 AN5 RC1 ANS4 AN4 RC0 ANS3 AN3 RA4 ANS2 AN2 RA2 ANS1 AN1 RA1 ANS0 AN0 RA0
ANS11 AN11 RB5
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REGISTER 12-3: ADCON0 -- A/D CONTROL REGISTER (ADDRESS: 1Fh)
R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD CHS<3:0>: Analog Channel Select bits 0000 = Channel 00 (AN0) 0001 = Channel 01 (AN1) 0010 = Channel 02 (AN2) 0011 = Channel 03 (AN3) 0100 = Channel 04 (AN4) 0101 = Channel 05 (AN5) 0110 = Channel 06 (AN6) 0111 = Channel 07 (AN7) 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 = Channel 08 (AN8) Channel 09 (AN9) Channel 10 (AN10) Channel 11 (AN11) CVREF VR Reserved. Do not use. Reserved. Do not use. R/W-0 VCFG R/W-0 CHS3 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
bit 6
bit 5-2
bit 1
GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: A/D Conversion Status bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
REGISTER 12-4:
ADCON1 -- A/D CONTROL REGISTER 1 (ADDRESS: 9Fh)
U-0 -- bit 7 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7: bit 6-4:
Unimplemented: Read as `0' ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 Unimplemented: Read as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3-0:
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12.1.7 CONFIGURING THE A/D EXAMPLE 12-1: A/D CONVERSION
After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine sample time, see Section 18.0 "Electrical Specifications". After this sample time has elapsed the A/D conversion can be started. These steps should be followed for an A/D conversion: 1. Configure the A/D module: * Configure analog/digital I/O (ANSx) * Configure voltage reference (ADCON0) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON1) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit (PIR1<6>) * Set ADIE bit (PIE1<6>) * Set PEIE and GIE bits (INTCON<7:6>) Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0<1>) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared (with interrupts disabled); OR * Waiting for the A/D interrupt Read A/D Result register pair (ADRESH:ADRESL), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.
;This code block configures the A/D ;for polling, Vdd reference, R/C clock ;and RA0 input. ; ;Conversion start & wait for complete ;polling code included. ; BCF STATUS,RP1 ;Bank 1 BSF STATUS,RP0 ; MOVLW B'01110000' ;A/D RC clock MOVWF ADCON1 BSF TRISA,0 ;Set RA0 to input BSF ANSEL0,0 ;Set RA0 to analog BCF STATUS,RP0 ;Bank 0 MOVLW B'10000001' ;Right, Vdd Vref, AN0 MOVWF ADCON0 CALL SampleTime ;Wait min sample time BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI BSF STATUS,RP0 ;Bank 1 MOVF ADRESL,W ;Read lower 8 bits BCF STATUS,RP0 ;Bank 0 MOVWF RESULTLO
2.
3. 4. 5.
6. 7.
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12.2 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 12-4. The maximum recommended impedance for analog sources is 10 k. As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 12-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. To calculate the minimum acquisition time, TACQ, see the PICmicro(R) Mid-Range Reference Manual (DS33023).
EQUATION 12-1:
ACQUISITION TIME EXAMPLE
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + [ ( Temperature - 25C ) ( 0.05s/C ) ] Where CHOLD is charged to within 1/2 lsb:
1VAPPLIED 1 - ----------- = VCHOLD 2047
--------- RC VAPPLIED 1 - e = VCHOLD -------- 1RC VAPPLIED 1 - e = VAPPLIED 1 - ----------- 2047 - Tc - TC
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
Solving for TC:
TC = - CHOLD ( RIC + RSS + RS ) ln(1/2047) = - 10pF ( 1k + 7k + 10k ) ln(0.0004885) = 1.37 s
Therefore: TACQ = 2S + 1.37S + [ ( 50C- 25C ) ( 0.05S/C ) ] = 4.67S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
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FIGURE 12-4: ANALOG INPUT MODEL
VDD RS VA ANx CPIN 5 pF VT = 0.6V RIC 1k I LEAKAGE 500 nA Sampling Switch SS RSS CHOLD = DAC capacitance = 10 pF VSS
VT = 0.6V
Legend CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC)
6V 5V VDD 4V 3V 2V
RSS
5 6 7 8 9 10 11 Sampling Switch (k)
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12.3 A/D Operation During Sleep
The A/D converter module can operate during Sleep. This requires the A/D clock source to be set to the FRC option. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion. When the conversion is complete, the GO/DONE bit is cleared and the result is loaded into the ADRESH:ADRESL registers. If the A/D interrupt is enabled, the device awakens from Sleep. If the GIE bit (INTCON<7>) is set, the program counter is set to the interrupt vector (0004h). If GIE is clear, the next instruction is executed. If the A/D interrupt is not enabled, the A/D module is turned off, although the ADON bit remains set. When the A/D clock source is something other than RC, a SLEEP instruction causes the present conversion to be aborted and the A/D module is turned off. The ADON bit remains set.
FIGURE 12-5:
A/D TRANSFER FUNCTION
Full-Scale Range
3FFh 3FEh 3FDh A/D Output Code 3FCh 3FBh Full-Scale Transition 1 LSB ideal
004h 003h 002h 001h 000h 1 LSB ideal 0V Zero-Scale Transition VREF
Analog Input Voltage
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12.4 Effects of Reset
A device Reset forces all registers to their Reset state. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged. and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), then the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 counter. See Section 8.0 "Capture/Compare/PWM (CCP) Module" for more information.
12.5
Use of the CCP Trigger
An A/D conversion can be started by the "special event trigger" of the CCP module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion
TABLE 12-3:
Addr
05h, 105h 06h, 106h 07h, 107h 0Bh, 8Bh 0Ch 1Eh 1Fh 85h, 185h 86h, 186h 87h, 187h 8Ch 91h 93h 9Eh 9Fh
SUMMARY OF A/D REGISTERS
Bit 7
-- RB7 RC7 GIE EEIF
Name
PORTA PORTB PORTC INTCON PIR1 ADRESH ADCON0 TRISA TRISB TRISC PIE1 ANSEL0 ANSEL1 ADRESL ADCON1
Bit 6
-- RB6 RC6 PEIE ADIF
Bit 5
RA5 RB5 RC5 T0IE CCP1IF
Bit 4
RA4 RB4 RC4 INTE C2IF
Bit 3
RA3 -- RC3 RAIE C1IF
Bit 2
RA2 -- RC2 T0IF OSFIF
Bit 1
RA1 -- RC1 INTF TMR2IF
Bit 0
RA0 -- RC0 RAIF TMR1IF
Value on: POR, BOR
--xx xxxx xxxx ---xxxx xxxx 0000 0000 0000 0000 xxxx xxxx
Value on all other Resets
--uu uuuu uuuu ---uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 --11 1111 1111 ---1111 1111 0000 0000 1111 1111 ---- 1111 uuuu uuuu -000 ----
Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result ADFM -- TRISB7 TRISC7 EEIE ANS7 -- VCFG -- TRISB6 TRISC6 ADIE ANS6 -- CHS3 TRISA5 TRISB5 TRISC5 CCP1IE ANS5 -- CHS2 TRISA4 TRISB4 TRISC4 C2IE ANS4 -- CHS1 TRISA3 -- TRISC3 C1IE ANS3 ANS11 CHS0 TRISA2 -- TRISC2 OSFIE ANS2 ANS10 GO/DONE TRISA1 -- TRISC1 TMR2IE ANS1 ANS9 ADON TRISA0 -- TRISC0 TMR1IE ANS0 ANS8
0000 0000 --11 1111 1111 ---1111 1111 0000 0000 1111 1111 ---- 1111 xxxx xxxx
Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result -- ADCS2 ADCS1 ADCS0 -- -- -- --
-000 ----
Legend:
x = unknown, u = unchanged, -- = unimplemented read as '0'. Shaded cells are not used for A/D module.
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13.0 TWO-PHASE PWM
EQUATION 13-2: PHASE RESOLUTION
The two-phase PWM (Pulse Width Modulator) is a stand-alone peripheral that supports: * Single or dual-phase PWM * Single complementary output PWM with overlap/ delay * Sync input/output to cascade devices for additional phases Setting either, or both, of the PH1EN or PH2EN bits of the PWMCON0 register will activate the PWM module (see Register 13-1). If PH1 is used then TRISC<1> must be cleared to configure the pin as an output. The same is true for TRISC<4> when using PH2.
360 Phase DEG = ------------------------( PER + 1 )
13.3 PWM Duty Cycle
13.1
PWM Period
The PWM period is derived from the main clock (FOSC), the PWM prescaler and the period counter (see Figure 13-3). The prescale bits (PWMP<1:0>, see Register 13-2) determine the value of the clock divider which divides the system clock (FOSC) to the pwm_clk. This pwm_clk is used to drive the PWM counter. In Master mode, the PWM counter is reset when the count reaches the period count (PER<4:0>, see Register 13-2), which determines the frequency of the PWM. The relationship between the PWM frequency, prescale and period count is shown in Equation 13-1.
Each PWM output is driven inactive, terminating the drive period, by asynchronous feedback through the internal comparators. The duty cycle resolution is in effect infinitely adjustable. Either or both comparators can be used to reset the PWM by setting the corresponding comparator enable bit (CxEN, see Register 13-3). Duty cycles of 100% can be obtained by suppressing the feedback which would otherwise terminate the pulse. The comparator outputs can be "held off", or blanked, by enabling the corresponding BLANK bit (BLANKx, see Register 13-1) for each phase. The blank bit disables the comparator outputs for 1/2 of a system clock (FOSC), thus ensuring at least Tosc/2 active time for the PWM output. Blanking avoids early termination of the PWM output which may result due to switching transients at the beginning of the cycle.
13.4
Master/Slave Operation
EQUATION 13-1:
PWM FREQUENCY
Fosc PWM FREQ = --------------------------------------------------PWMP (2 ( PER + 1 ) )
The maximum PWM frequency is FOSC/2, since the period count must be greater than zero. In Slave mode, the period counter is reset by the SYNC input, which is the master device period counter reset. For proper operation, the slave period count should be equal to or greater than that of the master.
Multiple chips can operate together to achieve additional phases by operating one as the master and the others as slaves. When the PWM is configured as a master, the RB7/SYNC pin is an output and generates a high output for one pwm_clk period at the end of each PWM period (see Figure 13-4). When the PWM is configured as a slave, the RB7/ SYNC pin is an input. The high input from a master in this configuration resets the PWM period counter which synchronizes the slave unit at the end of each PWM period. Proper operation of a slave device requires a common external FOSC clock source to drive the master and slave. The PWM prescale value of the slave device must also be identical to that of the master. As mentioned previously, the slave period count value must be greater than or equal to that of the master. The PWM Counter will be reset and held at zero when both PH1EN and PH2EN (PWMCON0<1:0>) are false. If the PWM is configured as a slave, the PWM Counter will remain reset at zero until the first SYNC input is received.
13.2
PWM Phase
Each enabled phase output is driven active when the phase counter matches the corresponding PWM phase count (PH<4:0>, see Register 13-4 and Register 13-5). The phase output remains true until terminated by a feedback signal from either of the comparators or the auto shutdown activates. Phase granularity is a function of the period count value. For example, if PER<4:0> = 3, each output can be shifted in 90 steps (see Equation 13-2).
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13.5 Active PWM Output Level
The PWM output signal can be made active high or low by setting or resetting the corresponding POL bit (see Register 13-3 and Register 13-4). When POL is `1' the active output state is VOL. When POL is `0' the active output state is VOH. The PWMASE bit (see Register 13-2) is set by hardware when a shutdown event occurs. If automatic restarts are not enabled (PRSEN = 0, see Register 13-1), PWM operation will not resume until the PWMASE bit is cleared by firmware after the shutdown condition clears. The PWMASE bit can not be cleared as long as the shutdown condition exists. If automatic restarts are not enabled, the auto-shutdown mode can be forced by writing a `1' to the PWMASE bit. If automatic restarts are enabled (PRSEN = 1), the PWMASE bit is automatically cleared and PWM operation resumes when the auto-shutdown event clears (VIH on the RA2/AN2/T0CKI/INT/C1OUT pin).
13.6
Auto-Shutdown and Auto-Restart
When the PWM is enabled, the PWM outputs may be configured for auto-shutdown by setting the PASEN bit (see Register 13-1). VIL on the RA2/AN2/T0CKI/INT/ C1OUT pin will cause a shutdown event if auto-shutdown is enabled. An Auto-shutdown event immediately places the PWM outputs in the inactive state (see Section 13.5 "Active PWM Output Level") and the PWM phase and period counters are reset and held to zero.
FIGURE 13-3: 2 PHASE PWM SIMPLIFIED BLOCK DIAGRAM
PWMP<1:0> PH1EN PH2EN PWMASE FOSC MASTER S PHASE RES COUNTER 0 1 M 5 PER<4:0> pwm_count SYNC
/1,2,4,8
PRESCALE
pwm_clk
PWMPH1 PH1 BLANK1 PWMPH1<4:0> PWMASE PH1EN C1OUT C2OUT PWMPH1 PWMPH1 S Q R* *Reset dominant pha1
PWMPH2 PH2 BLANK2 PWMPH2<4:0> PWMASE PH2EN S Q R* *Reset dominant pha2
PWMPH2 PWMPH2
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REGISTER 13-1: PWM CONTROL REGISTER 0 (PWMCON0: 111h)
R/W-0 PRSEN bit 7 bit 7 R/W-0 PASEN R/W-0 BLANK2 R/W-0 BLANK1 R/W-0 SYNC1 R/W-0 SYNC0 R/W-0 PH2EN R/W-0 PH1EN bit 0
PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the PWMASE shutdown bit clears automatically once the shutdown condition goes away. The PWM restarts automatically 0 = Upon auto-shutdown, the PWMASE must be cleared in firmware to restart the PWM. PASEN: PWM Auto-Shutdown Enable bit 0 = PWM Auto-Shutdown is disabled 1 = VIL on INT pin will cause Auto-Shutdown event BLANK2: PH2 Blanking bit 1 = The PH2 pin is active for a minimum of 1/2 of an FOSC clock period after it is set 0 = The PH2 pin is reset as soon as the comparator trigger is active BLANK1: PH1 Blanking bit 1 = The PH1 pin is active for a minimum of 1/2 of an FOSC clock period after it is set 0 = The PH1 pin is reset as soon as the comparator trigger is active SYNC<1:0>: SYNC Pin Function bits 0X = SYNC pin not used for PWM. PWM acts as its own master. RB6/SYNC pin is available for general purpose I/O. 10 = SYNC pin acts as system slave, receiving the PWM counter reset pulse 11 = SYNC pin acts as system master, driving the PWM counter reset pulse PH2EN: PH2 pin enabled 1 = The PH2 pin is driven by the PWM signal 0 = The PH2 pin is not used for PWM functions PH1EN: PH1 pin enabled 1 = The PH1 pin is driven by the PWM signal 0 = The PH1 pin is not used for PWM functions
bit 6
bit 5
bit 4
bit 3-2
bit 1
bit 0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = bit is cleared x = bit is unknown
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REGISTER 13-2: PWM CLOCK CONTROL REGISTER (PWMCLK: 112h)
R/W-0 PWMASE bit 7 bit 7 R/W-0 PWMP1 R/W-0 PWMP0 R/W-0 PER4 R/W-0 PER3 R/W-0 PER2 R/W-0 PER1 R/W-0 PER0 bit 0
PWMASE: PWM Auto-Shutdown event Status bit 0 = PWM outputs are operating. 1 = A shutdown event has occured. PWM outputs are inactive. PWMP<1:0>: PWM Clock Prescaler bits 00 = PWM Clock = FOSC / 1 01 = PWM Clock = FOSC / 2 10 = PWM Clock = FOSC / 4 11 = PWM Clock = FOSC / 8 PER<4:0>: PWM Period bits 00000 = Not used. (Period = PWM clock x 1) 00001 = Period = PWM clock x 2 0.... = . . . 01111 = Period = PWM clock x 16 10000 = Period = PWM clock x 17 1.... = . . . 11110 = Period = PWM clock x 31 11111 = Period = PWM clock x 32
bit 6-5
bit 4-0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = bit is cleared x = bit is unknown
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REGISTER 13-3: PWM PHASE 1 CONTROL REGISTER (PWMPH1: 113h)
R/W-0 POL bit 7 bit 7 R/W-0 C2EN R/W-0 C1EN R/W-0 PH4 R/W-0 PH3 R/W-0 PH2 R/W-0 PH1 R/W-0 PH0 bit 0
POL: PH1 Output Polarity bit 1 = PH1 Pin is active low 0 = PH1 Pin is active high C2EN: Comparator 2 Enable bit 1 = PH1 is reset when C2OUT is high 0 = PH1 ignores Comparator 2 C1EN: Comparator1 Enable bit 1 = PH1 is reset when C1OUT is high 0 = PH1 ignores Comparator 1 PH<4:0>: PWM Phase bits 00000 = PH1 is synchronous with the PWM SYNC pulse 00001 = PH1 is delayed by 1 pwm_clk pulse ..... = . . . 11111 = PH1 is delayed by 31 pwm_clk pulses
bit 6
bit 5
bit 4-0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = bit is cleared x = bit is unknown
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REGISTER 13-4: PWM PHASE 2 CONTROL REGISTER (PWMPH2: 114h)
R/W-0 POL bit 7 bit 7 R/W-0 C2EN R/W-0 C1EN R/W-0 PH4 R/W-0 PH3 R/W-0 PH2 R/W-0 PH1 R/W-0 PH0 bit 0
POL: PH2 Output Polarity bit 1 = PH2 Pin is active low 0 = PH2 Pin is active high C2EN: Comparator 2 Enable bit 1 = PH2 is reset when C2OUT is high 0 = PH2 ignores Comparator 2 C1EN: Comparator1 Enable bit 1 = PH2 is reset when C1OUT is high 0 = PH2 ignores Comparator 1 PH<4:0>: PWM Phase bits 00000 = PH2 is synchronous with the PWM SYNC pulse 00001 = PH2 is delayed by 1 PWM clock pulse ..... = . . . 11111 = PH2 is delayed by 31 PWM clock pulse
bit 6
bit 5
bit 4-0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = bit is cleared x = bit is unknown
FIGURE 13-4: 2 PHASE PWM SYSTEM TIMING
FOSC PWMP<1:0>=0X01, PER<4:0>=0X03 pwm_clk pwm_count SYNC Phase 1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0 pha1 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1
C1OUT Phase2 setup: PH<4:0> = 0x02, C2EN = 1, BLANK2 = 1 pha2
C2OUT
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FIGURE 13-5: 2 PHASE PWM AUTO-SHUTDOWN AND SYNC TIMING
FOSC PWMP<1:0> = 0X01, PER<4:0> = 0X03 pwm_clk MASTER pwm_count SYNC Phase1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0 pha1 0 1 2 0 1 2 3 0 1 2 3 0
SHUTDOWN pwm_clk SLAVE pwm_count 0 1 2 0 1 2 3 0 1 2 3 0
Phase2 setup: PH<4:0> = 0x02, C2EN = 1, BLANK2 = 1 pha2
FIGURE 13-6: 2 PHASE PWM START UP TIMING
FOSC PWMP<1:0> = 0X01, PER<4:0> = 0X03 pwm_clk MASTER pwm_count SYNC PHnEN 0 1 2 3 0 1 2 0
pwm_clk SLAVE pwm_count PHnEN 0 1 2 3 0 1 2 3
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13.7 Example single phase application
Figure 13-7 shows an example of a single phase buck voltage regulator application. The PWM output drives Q1 with pulses to alternately charge and discharge L1. C4 holds the charge from L1 during the inactive cycle of the drive period. R4 and C3 form a ramp generator. At the beginning of the PWM period, the PWM output goes high causing the voltage on C3 to rise concurrently with the current in L1. When the voltage across C3 reaches the threshold level present at the positive input of comparator 1, the comparator output changes and terminates the drive output from the PWM to Q1. When Q1 is not driven, the current path to L1 through Q1 is interrupted, but since the current in L1 cannot stop instantly, the current continues to flow through D2 as L1 discharges into C4. D1 quickly discharges C3 in preparation of the next ramp cycle. Resistor divider R5 and R6 scale the output voltage, which is inverted and amplified by Op Amp 1 relative to the reference voltage present at the non-inverting pin of the op amp. R3, C5 and C2 form the inverting stabilization gain feedback of the amplifier. The VR reference supplies a stable reference to the non-inverting input of the op amp, which is tweaked by the voltage source created by a secondary time based PWM output of the CCP and R1 and C1. Output regulation occurs by the following principle: If the regulator output voltage is too low, then the voltage to the non-inverting input of comparator 1 will rise, resulting in a higher threshold voltage and consequently longer PWM drive pulses into Q1. If the output voltage is too high, then the voltage to the non-inverting input of comparator 1 will fall, resulting in shorter PWM drive pulses into Q1.
FIGURE 13-7: EXAMPLE SINGLE PHASE APPLICATION PIC16F785 CCP
R1 R2 C1
VR
OPA1
FOSC FET DRIVER
VUNREG
R3 C2 C5
2 PHASE PWM C1
PH1
Q1 L1 C4 D2
R4
D1 R5 C3 R6
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13.8 Complementary Output Mode
The 2 Phase PWM module may be configured to operate in a Complementary Output mode where PH1 and PH2 are always 180 degrees out-of-phase (see Figure 13-8). Three complementary modes are available and are selected by the COMOD<1:0> bits in the PWMCON1 register (see Register 13-5). The difference between the modes is the method by which the PH1 and PH2 outputs switch from the active to the inactive state during the PWM period. The Complementary Output mode facilitates driving series connected MOSFET drivers by providing overlap or deadband drive timing between each phase output (see Figure 13-9). Overlap or deadband times are selectable by the CMDLY<4:0> bits of the PWMCON1 register. Delays from 0 to 155 nanoseconds (typical) with a resolution of 5 nanoseconds (typical) are available. Selection between overlap or deadband delay is controlled by the OVRLP bit of the PWM control register (PWMCON1<7>).
REGISTER 13-5:
PWM CONTROL REGISTER 1 (PWMCON1: 110h)
R/W-0 OVRLP bit 7 R/W-0 R/W-0 COMOD1 COMOD0 R/W-0 CMDLY4 R/W-0 CMDLY3 R/W-0 CMDLY2 R/W-0 CMDLY1 R/W-0 CMDLY0 bit 0
bit 7
OVRLP: Delay Overlap Select bit 1 = Delay time is overlap time between PH1 and PH2 0 = Delay time is deadtime between PH1 and PH2 COMOD<1:0>: Complementary Mode Select bits 00 = Normal 2 phase operation. Complementary mode is disabled. 01 = Complementary operation. On time is terminated by C1OUT or C2OUT. 10 = Complementary operation. On time is terminated by PWMPH2<4:0>=pwm_count. 11 = Complementary operation. On time is terminated by PWMPH2<4:0>=pwm_count or C1OUT or C2OUT. CMDLY<4:0>: Typical complementary drive deadtime/overlap time. 00000 = Delay = 0. 00001 = Delay = 5 ns 00010 = Delay = 10 ns ..... = . . . 11111 = Delay = 155 ns
bit 6-5
bit 4-0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = bit is cleared x = bit is unknown
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FIGURE 13-8: COMPLEMENTARY OUTPUT PWM BLOCK DIAGRAM
PS<1:0> PER<4:0>
FOSC PRESCALE
SYNC pwm_clk PHASE COUNT 5
pwm_count OVRLP
PWMASE
PWMPH1 PWMPH1<4:0>
delay
5
0 S 1 Q 0 pha1 PH1
CMDLY<4:0>
5 PWMPH2<4:0> PWMPH1 C1OUT PWMPH1 C2OUT COMOD<1:0> SHUTDOWN 11 10 01
1
R
PWMPH2
delay
0 S 1 Q 0 1 R pha2 PH2
FIGURE 13-9: COMPLEMENTARY OUTPUT PWM TIMING
FOSC PWMP<1:0> = 0X01, PER<4:0> = 0X03 pwm_clk pwm_count SYNC C1OUT Phase 1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0, COMOD<1:0> = 0x01 pha1 pha2 Delay Delay Delay Delay 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1
OVRLP = 0
OVRLP = 1
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TABLE 13-1:
Address
98h 99h 119h 11Ah 110h 111h 112h 113h 114h
REGISTERS/BITS ASSOCIATED WITH PWM
Bit 7
-- C1VREN C1ON C2ON OVRLP PRSEN PWMASE POL POL
Name
REFCON VRCON CM1CON0 CM2CON0 PWMCON1 PWMCON0 PWMCLK PWMPH1 PWMPH2
Bit 6
-- C2VREN C1OUT C2OUT
Bit 5
BGST VRR C1OE C2OE
Bit 4
VRBB -- C1POL C2POL
Bit 3
VREN VR3 C1SP C2SP CMDLY3 SYNC1 PER3 PH3 PH3
Bit 2
VROE VR2 C1R C2R CMDLY2 SYNC0 PER2 PH2 PH2
Bit 1
CVROE VR1 C1CH1 C2CH1 CMDLY1 PH2EN PER1 PH1 PH1
Bit 0
-- VR0 C1CH0 C2CH0 CMDLY0 PH1EN PER0 PH0 PH0
Value on: POR, BOR
--00 000000- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Value on all other Resets
--00 000000- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
COMOD1 COMOD0 CMDLY4 PASEN PWMP1 C2EN C2EN BLANK2 PWMP0 C1EN C1EN BLANK1 PER4 PH4 PH4
Legend: x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by data PWM module.
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NOTES:
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14.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory: * * * * EECON1 EECON2 (not a physically implemented register) EEDAT EEADR The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to AC Specifications in Section 18.0 "Electrical Specifications" for exact limits. When the data memory is code-protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access the data EEPROM data and will read zeroes. Additional information on the data EEPROM is available in the PICmicro(R) Mid-Range Reference Manual, (DS33023).
EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. The PIC16F785 has 256 bytes of data EEPROM with an address range from 0h to FFh.
REGISTER 14-1:
EEDAT -- EEPROM DATA REGISTER (ADDRESS: 9Ah)
R/W-0 EEDAT7 bit 7 R/W-0 EEDAT6 R/W-0 EEDAT5 R/W-0 EEDAT4 R/W-0 EEDAT3 R/W-0 R/W-0 R/W-0 EEDAT0 bit 0 EEDAT2 EEDAT1
bit 7-0
EEDATn: Byte Value to Write to or Read From Data EEPROM bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 14-2:
EEADR -- EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
R/W-0 EEADR7 bit 7 R/W-0 EEADR6 R/W-0 EEADR5 R/W-0 EEADR4 R/W-0 EEADR3 R/W-0 R/W-0 R/W-0 bit 0 EEADR2 EEADR1 EEADR0
bit 7-0
EEADR: Specifies one of 256 locations for EEPROM Read/Write Operation bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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14.1 EECON1 AND EECON2 REGISTERS
operation. In these situations, following Reset, the user can check the WRERR bit, clear it and rewrite the location. The EEDAT and EEADR registers are cleared by a reset. Therefore, the EEDAT and EEADR registers will need to be re-initialized. Interrupt flag EEIF bit (PIR1<7>) is set when write is complete. This bit must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the data EEPROM write sequence. Note: The EECON1, EEDAT and EEADR registers should not be modified during a data EEPROM write (WR bit = `1').
EECON1 is the control register with four low-order bits physically implemented. The upper four bits are nonimplemented and read as `0's. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal
REGISTER 14-3:
EECON1 -- EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 7-4 bit 3
Unimplemented: Read as `0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOR reset) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set, not cleared, in software.) 0 = Does not initiate an EEPROM read Legend: S = Bit can only be set R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 2
bit 1
bit 0
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14.2 READING THE EEPROM DATA MEMORY
After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit (PIR1<7>) register must be cleared by software.
To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>), as shown in Example 14-1. The data is available, in the very next cycle, in the EEDAT register. Therefore, it can be read in the next instruction. EEDAT holds this value until another read, or until it is written to by the user (during a write operation).
14.4
WRITE VERIFY
EXAMPLE 14-1:
BSF BSF MOVLW MOVWF BSF MOVF
DATA EEPROM READ
STATUS,RP0 ;Bank 1 STATUS,RP1 CONFIG_ADDR ; EEADR ;Address to read EECON1,RD ;EE Read EEDAT,W ;Move data to W
Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 14-3) to the desired value to be written.
EXAMPLE 14-3:
BSF BSF MOVF BSF XORWF BTFSS GOTO
WRITE VERIFY
14.3
WRITING TO THE EEPROM DATA MEMORY
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDAT register. Then the user must follow a specific sequence to initiate the write for each byte, as shown in Example 14-2.
STATUS,RP0 ;Bank 1 STATUS,RP1 EEDAT,W ;EEDAT not changed ; from previous write EECON1,RD ;YES, Read the ; value written EEDAT,W STATUS,Z ;Is data the same WRITE_ERR ;No, handle error ;Yes, continue
14.4.1 EXAMPLE 14-2:
BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF
USING THE DATA EEPROM
DATA EEPROM WRITE
;Bank 1 ;Enable write ;Disable INTs ;Unlock write ; ; ; ;Start the write ;Enable INTs
STATUS,RP0 STATUS,RP1 EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE
The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. A cycle count is executed during the required sequence. Any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the EEPROM. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware.
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM (specification D124) without excceding the total number of write cycles to a single byte (specifications D120 and D120A). If this is the case, then an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory.
Required Sequence
14.5
PROTECTION AGAINST SPURIOUS WRITE
There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: * brown-out * power glitch * software malfunction
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14.6 DATA EEPROM OPERATION DURING CODE-PROTECT
Data memory can be code-protected by programming the CPD bit in the Configuration Word (Register 15-1) to `0'. When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations in program memory to `0' will also help prevent data memory code protection from becoming breached.
TABLE 14-1:
Address 0Bh, 8Bh 0Ch 8Ch 9Ah 9Bh 9Ch 9Dh
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Bit 7 GIE EEIF EEIE Bit 6 PEIE ADIF ADIE Bit 5 T0IE CCP1IF CCP1IE Bit 4 INTE C2IF C2IE Bit 3 RAIE C1IF C1IE Bit 2 T0IF OSFIF OSFIE Bit 1 INTF Bit 0 RAIF Value on: POR, BOR Value on all other Resets
Name INTCON PIR1 PIE1 EEDAT EEADR EECON1 EECON2
0000 0000 0000 0000
TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 -- -- -- -- WRERR WREN WR RD ---- x000 ---- q000 ---- ---- ---- ----
EEPROM Control register 2 (not a physical register)
Legend: x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by data EEPROM module.
DS41249A-page 102
Preliminary
2004 Microchip Technology Inc.
PIC16F785
15.0 SPECIAL FEATURES OF THE CPU
15.1 Configuration Bits
The configuration bits can be programmed (read as `0'), or left unprogrammed (read as '1') to select various device configurations as shown in Register 15-1. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h - 3FFFh), which can be accessed only during programming. See PIC16F785 Memory Programming Specification (DS41237) for more information.
The PIC16F785 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Oscillator selection * Sleep * Code protection * ID Locations * In-Circuit Serial ProgrammingTM (ISCPTM) The PIC16F785 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Powerup Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power-up Timer to provide at least a 64 ms Reset. With these three functions onchip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low current Power-down mode. The user can wake-up from Sleep through: * External Reset * Watchdog Timer Wake-up * An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options (see Register 15-1).
15.2
Calibration Bits
The Brown-out Reset (BOR), Power-on Reset (POR), 8 MHz internal oscillator (HFINTOSC), Bandgap Offset (BGOFF) and Bandgap Temperature Compensation (BGTMP) are factory calibrated and should not be altered. These calibration values are stored in five calibration words which are mapped in program memory locations 2008h and 2009h respectively. The calibration words are not erased when the device is erased when using the procedure described in the PIC16F785 Memory Programming Specification (DS41237). Therefore, it is not necessary to store and reprogram these values when the device is erased.
Note:
Addresses 2008h and 2009h are beyond the user program memory space. They belong to the special configuration memory space (2000h - 3FFFh), which can be accessed only during programming. See PIC16F785 Memory Programming Specification (DS41237) for more information.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 103
PIC16F785
REGISTER 15-1:
-- bit 13 bit 13-12 bit 11 Unimplemented: Read as `1' FCMEN: Fail Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit (PCON<4>) 00 = BOR disabled CPD: Data Code Protection bit(2,3) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: RA3/MCLR pin function select bit(4) 1 = RA3/MCLR pin function is MCLR 0 = RA3/MCLR pin function is digital input, MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>) FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN 110 = RCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN 011 = EC: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, CLKIN on RA5/T1CKI/OSC1/CLKIN 010 = HS oscillator: High speed crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN 000 = LP oscillator: Low power crystal on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN Note 1: 2: 3: 4: Enabling Brown-out Reset does not automatically enable Power-up Timer. Program memory bulk erase must be performed to turned off code protection. The entire data EEPROM will be erased when the code protection is turned off. When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. --
CONFIG -- CONFIGURATION WORD (ADDRESS: 2007h)
IESO BOREN1 BOREN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 0
FCMEN
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
DS41249A-page 104
Preliminary
2004 Microchip Technology Inc.
PIC16F785
15.3 Reset
The PIC16F785 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 15-2. These bits are used in software to determine the nature of the Reset. See Table 15-4 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 15-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 18.0 "Electrical Specifications" for pulse width specifications.
Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * * Power-on Reset MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Reset (BOR)
FIGURE 15-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/VPP pin SLEEP WDT Module VDD Rise Detect VDD Brown-out(1) Reset Power-on Reset BOREN SBOREN WDT Time-out Reset
S
OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKI pin PWRT LFINTOSC 11-bit Ripple Counter R Q Chip_Reset
Enable PWRT Enable OST
Note 1:
Refer to the Configuration Word register (Register 15-1).
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 105
PIC16F785
15.3.1 POWER-ON RESET FIGURE 15-2:
VDD
The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A minimum rise time for VDD is required. See Section 18.0 "Electrical Specifications" for details. If the BOR is enabled, the minimum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 15.3.4 "Brown-Out Reset (BOR)") The POR circuit on this device has a POR re-arm circuit. This circuit is designed to ensure a re-arm of the POR circuit if VDD drops below a preset re-arming voltage (VPARM) for at least the minimum required time. Once VDD has been below the re-arming point for the minimum required time, the POR reset will reactivate and remain in reset until VDD returns to a value greater than VPOR. At this point, a 1s (typical) delay will be initiated to allow VDD to continue to ramp to a voltage safely above VPOR. When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to the "Power-up Trouble Shooting" Application Note (DS00607).
RECOMMENDED MCLR CIRCUIT
PIC16F785
R1 1 k (or greater) MCLR C1 0.1 F (optional, not critical)
15.3.3
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal) time out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the 31 kHz LFINTOSC oscillator. For more information, see Section 3.4 "Internal Clock Modes". The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE can disable (if `1') or enable (if `0') the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Time delay will vary from chip-to-chip and vary due to: * VDD variation * Temperature variation * Process variation See DC parameters for details "Electrical Specifications"). (Section 18.0
15.3.2
MASTER CLEAR (MCLR)
PIC16F785 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from early devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 15-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word. When cleared, MCLR is internally tied to VDD and an internal Weak Pull-up is enabled for the MCLR pin. In-Circuit Serial Programming is not affected by selecting the internal MCLR option.
DS41249A-page 106
Preliminary
2004 Microchip Technology Inc.
PIC16F785
15.3.4 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration Word select one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit (PCON<4>) enables/disables the BOR allowing it to be controlled in software. By selecting BOREN<1:0>, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBOREN bit is disabled. See Register 15-1 for the Configuration Word definition. If VDD falls below VBOR for greater than parameter (TBOR), see Section 18.0 "Electrical Specifications", the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not assured if VDD falls below VBOR for less than parameter (TBOR). On any Reset (Power-on, Brown-out Reset, Watchdog, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 15-3). The Power-up Timer will now be invoked, if enabled, and will keep the chip in Reset an additional 64 ms. Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset.
15.3.5
BOR CALIBRATION
The PIC16F785 stores the BOR calibration values in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the PIC16F785 Memory Programming Specification (DS41237) and thus, does not require reprogramming. Note: Address 2008h is beyond the user program memory space. It belongs to the special configuration memory space (2000h - 3FFFh), which can be accessed only during programming. See PIC16F785 Memory Programming Specification (DS41237) for more information.
FIGURE 15-3:
VDD
BROWN-OUT SITUATIONS
VBOR
Internal Reset VDD
64 ms(1)
VBOR <64 ms
Internal Reset
64 ms(1)
VDD
VBOR
Internal Reset
64 ms(1)
Note 1:
64 ms delay only if PWRTE bit is programmed to `0'.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 107
PIC16F785
15.3.6 TIME-OUT SEQUENCE 15.3.7
On power-up, the time-out sequence is as follows: first, PWRT time out is invoked after POR has expired, then OST is activated after the PWRT time out has expired. The total time out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit equal to `1' (PWRT disabled), there will be no time out at all. Figure 15-4, Figure 15-5 and Figure 15-6 depict time-out sequences. The device can execute code from the INTOSC, while OST is active by enabling Two-Speed Start-up or Fail-Safe Monitor (See Section 3.6.2 "Two-Speed Start-up Sequence" and Section 3.7 "Fail-Safe Clock Monitor"). Since the time outs occur from the POR pulse, if MCLR is kept low long enough, the time outs will expire. Then bringing MCLR high will begin execution immediately (see Figure 15-5). This is useful for testing purposes or to synchronize more than one PIC16F785 device operating in parallel. Table 15-5 shows the Reset conditions for some special registers, while Table 15-4 shows the Reset conditions for all the registers.
POWER CONTROL (PCON) REGISTER
The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOR (Brown-out Reset). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word). Bit 1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent Reset, if POR is `0', it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 15.3.4 "Brown-Out Reset (BOR)".
TABLE 15-1:
TIME OUT IN VARIOUS SITUATIONS
Power-up Brown-out Reset PWRTE = 0 TPWRT + 1024*TOSC TPWRT PWRTE = 1 1024*TOSC -- Wake-up from Sleep 1024*TOSC --
Oscillator Configuration PWRTE = 0 XT, HS, LP RC, EC, INTOSC TPWRT + 1024*TOSC TPWRT PWRTE = 1 1024*TOSC --
TABLE 15-2:
POR 0 1 u u u u
STATUS/PCON BITS AND THEIR SIGNIFICANCE
TO 1 1 0 0 u 1 PD 1 1 u 0 u 0 Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep Condition
BOR x 0 u u u u
Legend: u = unchanged, x = unknown
TABLE 15-3:
Address Name
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Bit 7 IRP -- Bit 6 RP1 -- Bit 5 RPO -- Bit 4 TO SBOREN Bit 3 PD -- Bit 2 Z -- Bit 1 DC POR Bit 0 C BOR Value on: POR, BOR 0001 1xxx ---1 --qq Value on all other Resets(1) 000q quuu ---u --uu
03h, 103h STATUS 83h, 183h 8Eh Legend: Note 1: PCON
u = unchanged, x = unknown, -- = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by BOR. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
DS41249A-page 108
Preliminary
2004 Microchip Technology Inc.
PIC16F785
FIGURE 15-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD MCLR Internal POR TPWRT PWRT Time Out
TOST
OST Time Out
Internal Reset
FIGURE 15-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
VDD MCLR Internal POR TPWRT PWRT Time Out
TOST
OST Time Out
Internal Reset
FIGURE 15-6:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
TPWRT PWRT Time Out
TOST
OST Time Out
Internal Reset
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 109
PIC16F785
TABLE 15-4:
Register
INITIALIZATION CONDITION FOR REGISTERS
Address Power-on Reset xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --x0 x000(6) xx00 ----(6) 00xx 0000(6) ---0 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 -000 0000 xxxx xxxx xxxx xxxx --00 0000 ---0 1000 xxxx xxxx 0000 0000 1111 1111 --11 1111 1111 ---1111 1111 0000 0000 ---1 --0x -110 x000 ---0 0000 1111 1111 1111 1111 * MCLR Reset * WDT Reset * Brown-out Reset(1) uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 000q quuu uuuu uuuu --0u 0uuu(7) 00uu ----(7) uu00 uuuu(7) ---0 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 -000 0000 uuuu uuuu uuuu uuuu --00 0000 ---0 1000 uuuu uuuu 0000 0000 1111 1111 --11 1111 1111 ---1111 1111 0000 0000 ---u --uq(1,5) -110 x000 ---u uuuu 1111 1111 1111 1111
(4)
* Wake-up from Sleep through interrupt * Wake-up from Sleep through WDT time out uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uuuu uuuu ---uuuu uuuu ---u uuuu uuuu uuuu(2) uuuu uuuu(2) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu ---uuuu uuuu uuuu uuuu ---u --uu -uuu uuuu ---u uuuu uuuu uuuu 1111 1111
W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON WDTCON ADRESH ADCON0 OPTION_REG TRISA TRISB TRISC PIE1 PCON OSCCON OSCTUNE ANSEL0 PR2 Legend: Note 1: 2: 3: 4: 5: 6: 7:
-- 00h/80h 01h 02h/82h 03h/83h 04h/84h 05h 06h 07h 0Ah/8Ah 0Bh/8Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 15h 18h 1Eh 1Fh 81h 85h 86h 87h 8Ch 8Eh 8Fh 90h 91h 92h
u = unchanged, x = unknown, -- = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 15-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. Analog channels read 0 but data latches are unknown. Analog channels read 0 but data latches are unchanged.
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2004 Microchip Technology Inc.
PIC16F785
TABLE 15-4:
Register
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address Power-on Reset ---- 1111 --11 1111 --00 0000 --00 000000- 0000 0000 0000 0000 0000 ---- x000 ---- ---xxxx xxxx -000 ---0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00-- --10 0--- ---0--- ---* MCLR Reset * WDT Reset (Continued) * Brown-out Reset(1) ---- 1111 --11 1111 --00 0000 --00 000000- 0000 0000 0000 0000 0000 ---- q000 ---- ---uuuu uuuu -000 ---0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00-- --10 0--- ---0--- ---* Wake-up from Sleep through interrupt * Wake-up from Sleep through WDT time out ---- uuuu --uu uuuu --uu uuuu --uu uuuuuu- uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- ---uuuu uuuu -uuu ---uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-- --uu u--- ---u--- ----
ANSEL1 WPUA IOCA REFCON VRCON EEDAT EEADR EECON1 EECON2 ADRESL ADCON1 PWMCON1 PWMCON0 PWMCLK PWMPH1 PWMPH2 CM1CON0 CM2CON0 CM2CON1 OPA1CON OPA2CON Legend: Note 1: 2: 3: 4: 5: 6: 7:
93h 95h 96h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh 110h 111h 112h 113h 114h 119h 11Ah 11Bh 11Ch 11Dh
u = unchanged, x = unknown, -- = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 15-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. Analog channels read 0 but data latches are unknown. Analog channels read 0 but data latches are unchanged.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 111
PIC16F785
TABLE 15-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)
Status Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register ---1 --0x ---u --uu ---u --uu ---u --uu ---u --uu ---1 --10 ---u --uu
Legend: u = unchanged, x = unknown, -- = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.
DS41249A-page 112
Preliminary
2004 Microchip Technology Inc.
PIC16F785
15.4
* * * * * * * * * *
Interrupts
The PIC16F785 has 11 sources of interrupt: External Interrupt RA2/INT TMR0 Overflow Interrupt PORTA Change Interrupt 2 Comparator Interrupts A/D Interrupt Timer 1 Overflow Interrupt Timer 2 Match Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt CCP Interrupt
For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 15-8). The latency is the same for one or twocycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. For additional information on Timer1, Timer2, comparators, A/D, Data EEPROM or CCP modules, refer to the respective peripheral section.
The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. A Global Interrupt Enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register and PIE1 register. GIE is cleared on Reset. The Return from Interrupt instruction, RETFIE, exits interrupt routine, as well as sets the GIE bit, which reenables unmasked interrupts. The following interrupt flags are contained in the INTCON register: * INT Pin Interrupt * PORTA Change Interrupt * TMR0 Overflow Interrupt The peripheral interrupt flags are contained in the special register PIR1. The corresponding interrupt enable bit is contained in special register PIE1. The following interrupt flags are contained in the PIR1 register: * * * * * * * EEPROM Data Write Interrupt A/D Interrupt 2 Comparator Interrupts Timer1 Overflow Interrupt Timer 2 Match Interrupt Fail-Safe Clock Monitor Interrupt CCP Interrupt
When an interrupt is serviced: * The GIE is cleared to disable any further interrupt * The return address is pushed onto the stack * The PC is loaded with 0004h
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 113
PIC16F785
15.4.1 RA2/AN2/T0CKI/INT/C1OUT INTERRUPT 15.4.2 TMR0 INTERRUPT
External interrupt on RA2/AN2/T0CKI/INT/C1OUT pin is edge-triggered; either rising, if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RA2/AN2/T0CKI/ INT/C1OUT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the Interrupt Service Routine before reenabling this interrupt. The RA2/AN2/T0CKI/INT/ C1OUT interrupt can wake-up the processor from Sleep if the INTE bit was set prior to going into Sleep. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). See Section 15.7 "Power-Down Mode (Sleep)" for details on Sleep and Figure 15-10 for timing of wake-up from Sleep through RA2/AN2/ T0CKI/INT/C1OUT interrupt. Note: The ANSEL0 (91h), and ANSEL1 (93h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. See Section 5.0 "Timer0 Module" for operation of the Timer0 module.
15.4.3
PORTA INTERRUPT
An input change on PORTA change sets the RAIF (INTCON<0>) bit. The interrupt can be enabled/ disabled by setting/clearing the RAIE (INTCON<3>) bit. Plus, individual pins can be configured through the IOCA register. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.
FIGURE 15-7:
INTERRUPT LOGIC
IOC-RA0 IOCA0 IOC-RA1 IOCA1 IOC-RA2 IOCA2 IOC-RA3 IOCA3 IOC-RA4 IOCA4 IOC-RA5 IOCA5 TMR2IF TMR2IE TMR1IF TMR1IE C1IF C1IE C2IF C2IE ADIF ADIE EEIF EEIE OSFIF OSFIE CCP1IF CCP1IE T0IF T0IE INTF INTE RAIF RAIE PEIE GIE Wake-up (If in Sleep mode)
Interrupt to CPU
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Preliminary
2004 Microchip Technology Inc.
PIC16F785
FIGURE 15-8:
Q1 OSC1 CLKOUT (3)
(4)
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5:
(1) (5)
(1)
Interrupt Latency (2)
PC
PC+1 Inst (PC+1) Inst (PC)
PC+1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
Inst (PC) Inst (PC-1)
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3 - 4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 18.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4 - Q1 cycles.
TABLE 15-6:
Address Name
SUMMARY OF INTERRUPT REGISTERS
Bit 7 GIE EEIF EEIE Bit 6 PEIE ADIF ADIE Bit 5 T0IE CCP1IF CCP1IE Bit 4 INTE C2IF C2IE Bit 3 RAIE C1IF C1IE Bit 2 T0IF OSFIF OSFIE Bit 1 INTF Bit 0 RAIF Value on: POR, BOR Value on all other Resets
0Bh, 8Bh INTCON 0Ch 8Ch Legend: PIR1 PIE1
0000 0000 0000 0000
TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000
x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by the Interrupt module.
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15.5 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and Status registers). This must be implemented in software. Since the last 16 bytes of all banks are common in the PIC16F785 (See Figure 2-2), temporary holding registers W_TEMP and STATUS_TEMP should be placed in here. These 16 locations do not require banking therefore, making it easier to save and restore context. The same code shown in Example 15-1 can be used to: * * * * * Store the W register Store the Status register Execute the ISR code Restore the Status (and Bank Select Bit register) Restore the W register
Note:
The PIC16F785 normally does not require saving the PCLATH. However, if computed GOTO's are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR.
EXAMPLE 15-1:
MOVWF SWAPF CLRF MOVWF : :(ISR) : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
;Copy ;Swap ;bank ;Save W to TEMP register status to be saved into W (swap does not affect status) 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register
W_TEMP STATUS,W STATUS STATUS_TEMP
;Insert user code here STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into Status register ;Swap W_TEMP ;Swap W_TEMP into W
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15.6 Watchdog Timer (WDT)
For PIC16F785, the WDT has been modified from previous PIC16F devices. The new WDT is code and functionally compatible with previous PIC16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to scale the value for the WDT and TMR0 at the same time. In addition, the WDT timeout value can be extended to 268 seconds. WDT is cleared under certain conditions described in Table 15-7. A new prescaler has been added to the path between the INTRC and the multiplexers used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the INTRC by 128 to 65536, giving the time base used for the WDT a nominal range of 1 ms to 268s.
15.6.2
WDT CONTROL
The WDTE bit is located in the Configuration Word. When set, the WDT runs continuously. When the WDTE bit in the Configuration Word register is set, the SWDTEN bit (WDTCON<0>) has no effect. If WDTE is clear, then the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits (OPTION_REG) have the same function as in previous versions of the PIC16F family of microcontrollers. See Section 5.0 "Timer0 Module" for more information.
15.6.1
WDT OSCILLATOR
The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit does not reflect that the LFINTOSC is enabled (OSCON<1>). The value of WDTCON is `---0 1000' on all Resets. This gives a nominal time base of 16 ms, which is compatible with the time base generated with previous PIC16F microcontroller versions. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled).
FIGURE 15-9:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source 0 Prescaler(1) 16-bit WDT Prescaler 1 8 PSA
PS<2:0> TO TMR0 0 1 PSA
31 kHz LFINTOSC Clock
WDTPS<3:0>
WDTE from Configuration Word SWDTEN from WDTCON WDT Timeout
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 "Prescaler" for more information.
TABLE 15-7:
WDT STATUS
Conditions WDT
WDTE = 0 CLRWDT command OSC FAIL detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP
Cleared
Cleared until the end of OST
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REGISTER 15-2: WDTCON -- WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h)
U-0 -- bit 7 bit 7-5 bit 4-1 Unimplemented: Read as `0' WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved SWDTEN: Software Enable or Disable the Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE configuration bit = 0, then it is possible to turn WDT on/off with this control bit. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 WDTPS3 R/W-1 WDTPS2 R/W-0 WDTPS1 R/W-0 WDTPS0 R/W-0 SWDTEN bit 0
bit 0
TABLE 15-8:
Address 18h 81h/ 181h Legend: Note 1:
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7 -- RAPU CPD Bit 6 -- INTEDG CP Bit 5 -- T0CS Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on: all other POR,BOR resets ---0 1000
Name WDTCON OPTION_REG
WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 T0SE PSA WDTE PS2 FOSC2 PS1 FOSC1 PS0 FOSC0
1111 1111 1111 1111
uuuu uuuu uuuu uuuu
2007h(1) CONFIG
MCLRE PWRTE
Shaded cells are not used by the Watchdog Timer. See Register 15-1 for operation of all Configuration Word bits.
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15.7 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * WDT will be cleared but keeps running. PD bit in the Status register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit (and PIE bit where applicable) must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed.
For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin, and all unused peripheral modules should be disabled. Digital I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTA should be considered. The MCLR pin must be at a logic high level. Note: It should be noted that a Reset generated by a WDT time out does not drive MCLR pin low.
The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.
15.7.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set, and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
15.7.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin Watchdog Timer Wake-up (if WDT was enabled) Interrupt from RA2/AN2/T0CKI/INT/C1OUT pin, PORTA change or a peripheral interrupt.
The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the Status register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT Wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. 7. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP Capture mode interrupt A/D conversion (when A/D clock source is RC) EEPROM write operation completion Comparator output changes state Interrupt-on-change External Interrupt from INT pin
Other peripherals cannot generate interrupts since, during Sleep, no on-chip clocks are present.
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FIGURE 15-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Inst(PC) = Sleep Inst(PC - 1) Processor in Sleep Interrupt Latency (3)
PC+1 Inst(PC + 1) Sleep
PC+2
PC+2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy cycle
Dummy cycle
XT, HS or LP Oscillator mode assumed. TOST = 1024TOSC (drawing not to scale). This delay does not apply to EC, RC and INTOSC Oscillator modes. GIE = `1' assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = `0', execution will continue in-line. CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
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15.8 Code Protection
FIGURE 15-11:
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP for verification purposes. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off by performing a bulk erase. See the PIC16F785 Memory Programming Specification (DS41237) for more information.
External Connector Signals +5V 0V VPP
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections
*
PIC16F785 VDD VSS MCLR/VPP/RA3 RA1 RA0
15.9
ID Locations
CLK Data I/O
Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify. Only the Least Significant 7 bits of the ID locations are used.
*
*
*
15.10 In-Circuit Serial Programming
The PIC16F785 microcontrollers can be serially programmed while in the end application circuit. This is simply done with five lines: * * * * * clock data power ground programming voltage
To Normal Connections
* Isolation devices (as required)
This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RA0 and RA1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the PIC16F785 Memory Programming Specification (DS41237) for more information. RA0 becomes the programming data and RA1 becomes the programming clock. Both RA0 and RA1 are Schmitt Trigger inputs in this mode. After Reset, to place the device into Program/Verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. For complete details of serial programming, please refer to the PIC16F785 Memory Programming Specification (DS41237). A typical In-Circuit Serial Programming connection is shown in Figure 15-11.
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15.11 In-Circuit Debugger
In-circuit debugging requires clock, data and MCLR pins. A special 28-pin PIC16F785 ICD device is used with MPLAB(R) ICD 2 to provide separate clock, data and MCLR pins so that no pins are lost for these functions leaving all 18 of the PIC16F785 I/O pins available to the user during debug operation. This special ICD device is mounted on the top of a header and its signals are routed to the MPLAB ICD 2 connector. On the bottom of the header is a 20-pin socket that plugs into the user's target via the 20-pin stand-off connector. When the ICD pin on the PIC16F785 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 15-9 shows which features are consumed by the background debugger:
TABLE 15-9:
Resource I/O pins Stack
DEBUGGER RESOURCES
Description ICDCLK, ICDDATA 1 level Address 0h must be NOP 700h - 7FFh
Program Memory
For more information, see MPLAB(R) ICD 2 In-Circuit Debugger User's Guide (DS51292), available on Microchip's web site (www.microchip.com).
FIGURE 15-12:
28-Pin PDIP
28-PIN ICD PINOUT
In-Circuit Debug Device
SHNTREG ICDMCLR/VPP VDD RA5 RA4 RA3 RC5 RC4 RC3 RC6 RC7 RB7 ICD NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
ICDCLK ICDDATA Vss RA0 RA1 RA2 RC0 RC1 RC2 RB4 RB5 RB6 NC NC
PIC16F785 -ICD
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16.0 INSTRUCTION SET SUMMARY
The PIC16F785 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The format for each of the categories is presented in Figure 16-1, while the various opcode fields are summarized in Table 16-1. Table 16-2 lists the instructions recognized by the MPASMTM assembler. A complete description of each instruction is also available in the PICmicro(R) MidRange Reference Manual (DS33023). For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. Note: To maintain upward compatibility with future products, do not use the OPTION and TRIS instructions. For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended result of clearing the condition that set the RAIF flag.
TABLE 16-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
d
PC TO PD
FIGURE 16-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
0
All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
0
16.1
READ-MODIFY-WRITE OPERATIONS
0
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is always performed, even if the instruction is a write command.
k = 11-bit immediate value
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TABLE 16-2:
Mnemonic, Operands
PIC16F785 INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b k k k k k k k k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C,DC,Z Z TO,PD Z 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO,PD C,DC,Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023).
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16.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [label] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. k BCF Syntax: Operands: Operation: Status Affected: Description: Bit Clear f [label] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
BSF Syntax: ADDWF Syntax: Operands: Operation: Status Affected: Description: Add W and f [label] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is 0, the result is stored in the W register. If `d' is 1, the result is stored back in register `f'. BTFSC Syntax: Operands: Operation: ANDLW Syntax: Operands: Operation: Status Affected: Description: AND Literal with W [label] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k Status Affected: Description: f,d Operation: Status Affected: Description: Operands:
Bit Set f [label] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
Bit Test f, Skip if Clear [label] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f'' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction.
BTFSS Syntax:
Bit Test f, Skip if Set [label] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [label] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is 0, the result is stored in the W register. If `d' is 1, the result is stored back in register `f'. f,d
Operands: Operation: Status Affected: Description:
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CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. COMF Syntax: Operands: Operation: Status Affected: Description: Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is 0, the result is stored in W. If `d' is 1, the result is stored back in register `f'. f,d
Status Affected: Description:
DECF Syntax: Operands:
Decrement f [label] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is 0, the result is stored in the W register. If `d' is 1, the result is stored back in register `f'.
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [label] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. DECFSZ f Operation: Status Affected: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is 0, the result is placed in the W register. If `d' is 1, the result is placed back in register `f'. If the result is 1, the next instruction is executed. If the result is 0, then a NOP is executed instead, making it a 2-cycle instruction.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
Syntax: Operands: Operation: Status Affected: Description:
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Description:
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GOTO Syntax: Operands: Operation: Status Affected: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a twocycle instruction. IORLW Syntax: Operands: Operation: Status Affected: Description: Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
IORWF Syntax:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is 0, the result is placed in the W register. If `d' is 1, the result is placed back in register `f'.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is 0, the result is placed in the W register. If `d' is 1, the result is placed back in register `f'.
Operands: Operation: Status Affected: Description:
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff
INCFSZ Syntax: Operands: Operation: Status Affected: Description:
Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is 0, the result is placed in the W register. If `d' is 1, the result is placed back in register `f'. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead, making it a 2-cycle instruction.
The contents of register `f' is moved to a destination dependent upon the status of d. If `d' = 0, destination is W register. If `d' = 1, the destination is file register `f' itself. `d' = 1 is useful to test a file register since status flag Z is affected. 1 1
MOVF FSR, 0 W= register Z = value in FSR 1
Words: Cycles: Example
After Instruction
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NOP MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk
No Operation [ label ] None No operation None
00 0000 0xx0 0000
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
NOP
MOVLW k
0 k 255
No operation. 1 1
NOP
The eight bit literal `k' is loaded into W register. The don't cares will assemble as 0's. 1 1
MOVLW 0x5A
Words: Cycles: Example
After Instruction
W = 0x5A
RETFIE Syntax: Operands: Operation: f Status Affected: Encoding: Description:
Return from Interrupt [ label ] None TOS PC, 1 GIE None
00 0000 0000 1001
RETFIE
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff
MOVWF
0 f 127
Move data from W register to register `f'. 1 1
MOVWF OPTION OPTION = W = 0xFF 0x4F 0x4F 0x4F
Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
Words: Cycles: Example
Before Instruction
After Interrupt
PC = GIE = TOS 1
After Instruction
OPTION = W =
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RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff
RLF
f,d
The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction
W W = = 0x07 value of k8
Words: Cycles: Example
The contents of register `f' are rotated one bit to the left through the Carry Flag. If `d' is 0, the result is placed in the W register. If `d' is 1, the result is stored back in register `f'.
C Register f
Words: Cycles: Example
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
TABLE
Before Instruction
After Instruction
REG1 W C
After Instruction
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
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RRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff
SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Subtract W from Literal [label] 0 k 255 k - (W) (W) C, DC, Z
11 110x kkkk kkkk
SUBLW k
The contents of register `f' are rotated one bit to the right through the Carry Flag. If `d' is 0 the result is placed in the W register. If `d' is 1 the result is placed back in register `f'.
C REGISTER F
The W register is subtracted (2's complement method) from the eight bit literal `k'. The result is placed in the W register. 1 1
SUBLW 0x02
Words: Cycles: Example 1:
Words: Cycles: Example
1 1
RRF REG1, 0
Before Instruction W=1 C=? After Instruction W=1 C = 1; result is positive Example 2: Before Instruction W= 2 C=? After Instruction W= 0 C = 1; result is zero
Before Instruction REG1 = 1110 0110 C =0 After Instruction REG1 = 1110 0110 W = 0111 0011 C =0
SLEEP Syntax: Operands: Operation: [label] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011
SLEEP
Example 3:
Before Instruction W= C= W= C= 3 ? 0xFF 0; result is negative
After Instruction
Status Affected: Encoding: Description:
The power-down Status bit, PD is cleared. Time out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. 1 1
SLEEP
Words: Cycles: Example:
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SUBWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from f [label] 0 f 127 d [0,1] (f) - (W) (dest) C, DC, Z Status Affected:
00 0010 dfff ffff
SWAPF Syntax: Operands: Operation:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None
00 1110 dfff ffff
SUBWF f,d
Encoding: Description:
Subtract (2's complement method) W register from register `f'. If `d' is 0 the result is stored in the W register. If `d' is 1 the result is stored back in register `f'. 1 1
SUBWF REG1, 1
The upper and lower nibbles of register `f' are exchanged. If `d' is 0 the result is placed in W register. If `d' is 1 the result is placed in register `f'. 1 1
SWAPF REG1, 0
Words: Cycles: Example 1:
Words: Cycles: Example
Before Instruction REG1 = 3 W =2 C =? After Instruction REG1 W C Z DC Example 2: = = = = = 1 2 1; result is positive 0 1
Before Instruction REG1 = 0xA5 After Instruction REG1 = 0xA5 W = 0x5A
TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description:
Load TRIS Register [ label ] TRIS 5f6 (W) TRIS register f; None
00 0000 0110 0fff
f
Before Instruction REG1 = 2 W =2 C =? After Instruction REG1 W C Z = = = = 0 2 1; result is zero DC = 1
The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them. 1 1 To maintain upward compatibility with future PICmicro(R) products, do not use this instruction.
Example 3:
Before Instruction REG1 = 1 W =2 C =? After Instruction REG1 W C Z = = = = 0xFF 2 0; result is negative DC = 0
Words: Cycles: Example
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XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR Literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W) Z
11 1010 kkkk kkkk
XORWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR W with f [ label ] 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z
00 0110 dfff ffff
XORWF
f,d
The contents of the W register are XOR'ed with the eight bit literal `k'. The result is placed in the W register. 1 1
XORLW 0xAF
Words: Cycles: Example:
Exclusive OR the contents of the W register with register `f'. If `d' is 0 the result is stored in the W register. If `d' is 1 the result is stored back in register `f'. 1 1
XORWF REG1, 1
Words: Cycles: Example
Before Instruction W = 0xB5 After Instruction W = 0x1A
Before Instruction REG1 = 0xAF W = 0xB5 After Instruction REG1 = 0x1A W = 0xB5
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17.0 DEVELOPMENT SUPPORT
17.1
The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator - MPLAB dsPIC30 Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 4 Demonstration Board - PICDEM 17 Demonstration Board - PICDEM 18R Demonstration Board - PICDEM LIN Demonstration Board - PICDEM USB Demonstration Board * Evaluation Kits - KEELOQ(R) Security ICs - PICDEM MSC - microID(R) RFID - CAN - PowerSmart(R) Battery Management - Analog
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor with color coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Extensive on-line help The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files (assembly or C) - mixed assembly and C - machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increasing flexibility and power.
17.2
MPASM Assembler
The MPASM assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects * User defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
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17.3 MPLAB C17 and MPLAB C18 C Compilers 17.6 MPLAB ASM30 Assembler, Linker and Librarian
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 compiler uses the assembler to produce it's object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
17.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB object librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
17.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until Break or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers, as well as the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.
17.5
MPLAB C30 C Compiler
17.8
MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI compliant, optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. The compiler also supports many command line options and language extensions to take full advantage of the dsPIC30F device hardware capabilities and afford fine control of the compiler code generator. MPLAB C30 is distributed with a complete ANSI C standard library. All library functions have been validated and conform to the ANSI C library standard. The library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high-level source debugging with the MPLAB IDE.
The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines.
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17.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator 17.11 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro microcontrollers. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost effective in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real-time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices.
The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
17.12 PRO MATE II Universal Device Programmer
The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the PRO MATE II device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode.
17.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICD 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, up to 2 Mb of emulation memory and the ability to view variables in real-time. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
17.13 MPLAB PM3 Device Programmer
The MPLAB PM3 is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Standalone mode, the MPLAB PM3 device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode. MPLAB PM3 connects to the host PC via an RS232 or USB cable. MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
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17.14 PICSTART Plus Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
17.17 PICDEM 2 Plus Demonstration Board
The PICDEM 2 Plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or MPLAB ICD 2 with a Universal Programmer Adapter. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2 x 16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs and sample PIC18F452 and PIC16F877 Flash microcontrollers.
17.15 PICDEM 1 PICmicro Demonstration Board
The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer or a PICSTART Plus development programmer. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional application components. Features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs.
17.18 PICDEM 3 PIC16C92X Demonstration Board
The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package. All the necessary hardware and software is included to run the demonstration programs.
17.19 PICDEM 4 8/14/18-Pin Demonstration Board
The PICDEM 4 can be used to demonstrate the capabilities of the 8, 14 and 18-pin PIC16XXXX and PIC18XXXX MCUs, including the PIC16F818/819, PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to showcase the many features of these low pin count parts, including LIN and Motor Control using ECCP. Special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow onboard hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, DB-9 RS-232 interface, ICD connector for programming via ICSP and development with MPLAB ICD 2, 2 x 16 liquid crystal display, PCB footprints for HBridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User's Guide.
17.16 PICDEM.net Internet/Ethernet Demonstration Board
The PICDEM.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. This kit features a user friendly TCP/IP stack, web server with HTML, a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface and a 16 x 2 LCD display. Also included is the book and CD-ROM "TCP/IP Lean, Web Servers for Embedded Systems," by Jeremy Bentham
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17.20 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion.
17.24 PICDEM USB PIC16C7X5 Demonstration Board
The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. This board provides the basis for future USB products.
17.25 Evaluation and Programming Tools
In addition to the PICDEM series of circuits, Microchip has a line of evaluation kits and demonstration software for these products. * KEELOQ evaluation and programming tools for Microchip's HCS Secure Data Products * CAN developers kit for automotive network applications * Analog design boards and filter design software * PowerSmart battery charging evaluation/ calibration kits * IrDA(R) development kit * microID development and rfLabTM development software * SEEVAL(R) designer kit for memory evaluation and endurance calculations * PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits.
17.21 PICDEM 18R PIC18C601/801 Demonstration Board
The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/Demultiplexed and 16-bit Memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801.
17.22 PICDEM LIN PIC16C43X Demonstration Board
The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication.
17.23 PICkitTM 1 Flash Starter Kit
A complete "development system in a box", the PICkit Flash Starter Kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin Flash PIC(R) microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the User's Guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB(R) IDE (Integrated Development Environment) software, software and hardware "Tips 'n Tricks for 8-pin Flash PIC(R) Microcontrollers" Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices.
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18.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings() Ambient temperature under bias........................................................................................................... -40 to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ...................................................................................................... -0.3 to +6.5V Voltage on MCLR with respect to Vss ..................................................................................................-0.3 to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) (PDIP and SOIC)................................................................................................... 800 mW Total power dissipation(1) (SSOP) .................................................................................................................. 600 mW Maximum current out of VSS pin ..................................................................................................................... 300 mA Maximum current into VDD pin ........................................................................................................................ 250 mA Input clamp current, IIK (VI < 0 or VI > VDD)................................................................................................................20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)..........................................................................................................20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by PORTA, PORTB, and PORTC (combined) ........................................................... 200 mA Maximum current sourced PORTA, PORTB, and PORTC (combined)........................................................... 200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under `Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 139
PIC16F785
FIGURE 18-1: PIC16F785 WITH ANALOG DISABLED VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20
Frequency (MHz) Note: The shaded region indicates the permissible combinations of voltage and frequency.
DS41249A-page 140
Preliminary
2004 Microchip Technology Inc.
PIC16F785
18.1 DC Characteristics: PIC16F785 -I (Industrial), PIC16F785 -E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions FOSC 4 MHz: PIC16F785 with A/D off PIC16F785 with A/D on, 0C to +125C PIC16F785 with A/D on, -40C to +125C 4 MHz FOSC 10 MHz 10 MHz FOSC 20 MHz Device in Sleep mode See Section 15.3.1 "Power-On Reset" for details. See Section 15.3.1 "Power-On Reset" for details.
DC CHARACTERISTICS Param No. D001 D001A D001B D001C D001D D002 D003 VDR VPOR RAM Data Retention Voltage(1) VDD voltage above which the internal POR releases VDD voltage below which the internal POR rearms VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset
Sym VDD
Characteristic Supply Voltage
2.0 2.2 2.5 3.0 4.5 1.5* -- -- 0.05*
-- -- -- -- -- -- 1.8 1.0 --
5.5 5.5 5.5 5.5 5.5 -- -- -- --
V V V V V V V V
D003A VPARM D004 SVDD
V/ms See Section 15.3.1 "Power-On Reset" for details. V
D005
VBOR
--
2.1
--
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 141
PIC16F785
18.2 DC Characteristics: PIC16F785-I (Industrial)(1,2)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Device Characteristics Supply Current (IDD) Min -- -- -- D011 -- -- -- D012 -- -- -- D013 -- -- -- D014 -- -- -- D015 -- -- -- D016 -- -- -- D017 -- -- -- D018 -- -- Typ 9 18 35 110 190 330 220 370 0.6 70 140 260 180 320 580 9 18 35 340 500 0.8 180 320 580 2.1 2.4 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD A A A A A A A A mA A A A A A A A A mA A A mA A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode FOSC = 4 MHz INTOSC mode FOSC = 31 kHz INTRC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32 kHz LP Oscillator mode
DC Characteristics Param No. D010
Legend: TBD = To Be Determined.
Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: 2:
3:
4:
The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the A/D module.
DS41249A-page 142
Preliminary
2004 Microchip Technology Inc.
PIC16F785
18.2 DC Characteristics: PIC16F785-I (Industrial)(1,2) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Device Characteristics Power-down Base Current (IPD)(4) Min -- -- -- D021 -- -- -- D022 D023 -- -- -- -- -- D023A -- -- -- D024 -- -- -- D024A -- -- -- D025 -- -- -- D026 D027 -- -- -- -- -- D028 -- -- Typ 8 16 33 0.3 1.8 8.4 58 109 3.3 6.1 200 3.3 6.1 35 58 85 104 58 85 78 4.0 4.6 6.0 1.2 2.2 8 10 12 150 250 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD nA nA nA A A A A A A A A A A A A A A A A A A A A nA nA A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 Op Amp Current(3) A/D Current(3) (not converting) VR Current(3) T1 OSC Current(3) CVREF Current(3) High Range CVREF Current(3) Low Range Comparator Current(3) CxSP = 0 Comparator Current(3) CxSP = 1 BOR Current(3) WDT Current(3) Note WDT, BOR, Comparators, VREF, T1OSC, Op Amps and VR disabled DC Characteristics Param No. D020
Legend: TBD = To Be Determined.
Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: 2:
3:
4:
The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the A/D module.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 143
PIC16F785
18.3 DC Characteristics: PIC16F785-E (Extended)(1,2)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Device Characteristics Supply Current (IDD) Min -- -- -- D011E -- -- -- D012E -- -- -- D013E -- -- -- D014E -- -- -- D015E -- -- -- D016E -- -- -- D017E -- -- -- D018E -- -- Typ 9 18 35 110 190 330 220 370 0.6 70 140 260 180 320 580 9 18 35 340 500 0.8 180 320 580 2.1 2.4 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD A A A A A A A A mA A A A A A A A A mA A A mA A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode FOSC = 4 MHz INTOSC mode FOSC = 31 kHz INTRC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32 kHz LP Oscillator mode
DC Characteristics Param No. D010E
Legend: TBD = To Be Determined
Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: 2:
3:
4:
The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the A/D module.
DS41249A-page 144
Preliminary
2004 Microchip Technology Inc.
PIC16F785
18.3 DC Characteristics: PIC16F785-E (Extended)(1,2) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Device Characteristics Power-down Base Current (IPD)(4) Min -- -- -- D021E -- -- -- D022E D023E -- -- -- -- -- D023E -- -- -- D024E -- -- -- D024E -- -- -- D025E -- -- -- D026E D027E -- -- -- -- -- D028E -- -- Typ 8 16 33 0.3 1.8 8.4 58 109 3.3 6.1 200 3.3 6.1 35 58 85 104 58 85 78 4.0 4.6 6.0 1.2 2.2 8 10 12 150 250 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 25 25 TBD TBD Units VDD nA nA nA A A A A A A A A A A A A A A A A A A A A nA nA A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 3.0 3.0 5.0 3.0 5.0 Op Amp Current(3) A/D Current(3) (not converting) VR Current(3) T1 OSC Current(3) CVREF Current(3) High Range CVREF Current(3) Low Range Comparator Current(3) CxSP = 0 Comparator Current(3) CxSP = 1 BOR Current(3) WDT Current(3) Note WDT, BOR, Comparators, VREF, T1OSC, Op Amps and VR disabled DC Characteristics Param No. D020E
Legend: TBD = To Be Determined
Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: 2:
3:
4:
The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the A/D module.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 145
PIC16F785
18.4 DC Characteristics: PIC16F785 -I (Industrial), PIC16F785 -E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym
Characteristic
Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (XT and LP modes)(1) OSC1 (HS mode)(1)
VIL D030 D030A D031 D032 D033 D033A VIH D040 D040A D041 D042 D043 D043A D043B D070 IPUR
VSS VSS VSS VSS VSS VSS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- 250
0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD
V V V V V V
4.5V VDD 5.5V Otherwise Entire range
Input High Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR OSC1 (XT and LP modes) OSC1 (HS mode) OSC1 (RC mode) PORTA Weak Pull-up Current Input Leakage Current(2) I/O ports Analog inputs VREF MCLR(3) OSC1 Output Low Voltage I/O ports OSC2/CLKOUT (RC mode) Output High Voltage I/O ports OSC2/CLKOUT (RC mode)
2.0 (0.25 VDD + 0.8) 0.8 VDD 0.8 VDD 1.6 0.7 VDD 0.9 VDD 50*
VDD VDD VDD VDD VDD VDD VDD 400*
V V V V V V V A
4.5V VDD 5.5V Otherwise Entire range (Note 1) (Note 1) VDD = 5.0V, VPIN = VSS
D060 D060A D060B D061 D063
IIL
-- -- -- -- --
0.1 0.1 0.1 0.1 0.1
1 1 1 5 5
A
A A A A
VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V (Ind.) IOL = 1.2 mA, VDD = 4.5V (Ext.) IOH = -3.0 mA, VDD = 4.5V IOH = -1.3 mA, VDD = 4.5V (Ind.) IOH = -1.0 mA, VDD = 4.5V (Ext.)
D080 D083
VOL
-- --
-- --
0.6 0.6
V V
D090 D092
VOH
VDD - 0.7 VDD - 0.7
-- --
-- --
V V
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
DS41249A-page 146
Preliminary
2004 Microchip Technology Inc.
PIC16F785
18.4 DC Characteristics: PIC16F785 -I (Industrial), PIC16F785 -E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions DC CHARACTERISTICS Param No.
Sym
Characteristic
D100
Capacitive Loading Specs on Output Pins COSC OSC2 pin 2 CIO
--
--
15*
pF
In XT, HS and LP modes when external clock is used to drive OSC1
D101
All I/O pins Data EEPROM Memory D120 ED Byte Endurance Byte Endurance D120A ED D121 VDRW VDD for Read/Write
-- 100K 10K VMIN
-- 1M 100K --
50* -- -- 5.5
pF E/W -40C TA +85C E/W +85C TA +125C V Using EECON1 to read/write VMIN = Minimum operating voltage ms Year Provided no other specifications are violated E/W -40C TA +85C
D122 D123 D124
TDEW Erase/Write cycle time TRETD Characteristic Retention TREF Number of Total Erase/ Write Cycles before Refresh(1) Program Flash Memory Cell Endurance Cell Endurance VDD for Read
-- 40 1M
5 -- 10M
6 -- --
D130 EP D130A EP D131 VPR D132 D133 D134
10K 1K VMIN 4.5 -- 40
100K 10K -- -- 2 --
-- -- 5.5 5.5 2.5 --
VPEW VDD for Erase/Write TPEW Erase/Write cycle time TRETD Characteristic Retention
E/W -40C TA +85C E/W +85C TA +125C V VMIN = Minimum operating voltage V ms Year Provided no other specifications are violated
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 147
PIC16F785
18.5 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid High-impedance
FIGURE 18-2:
LOAD CONDITIONS
Load Condition 1 VDD/2 Load Condition 2
RL
Pin VSS
RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins for OSC2 output
FIGURE 18-3:
EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKOUT 3 3 4 4
DS41249A-page 148
Preliminary
2004 Microchip Technology Inc.
PIC16F785
TABLE 18-1:
Param No. Sym FOSC
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency(1) Min -- DC DC DC -- -- DC 0.1 1 -- 50 50 250 Oscillator Period(1) -- -- 250 250 50 Typ 32.768 -- -- -- 32.768 4 -- -- -- 0.3052 -- -- -- 0.3052 250 -- -- -- Max -- 4 20 20 -- -- 4 4 20 -- -- -- -- 10,000 1,000 Units kHz MHz MHz MHz kHz MHz MHz MHz MHz s ns ns ns s ns ns ns ns Conditions LP mode (complementary input only) XT mode HS mode EC mode LP Osc mode INTOSC mode RC Osc mode XT Osc mode HS Osc mode LP mode (complementary input only) HS Osc mode EC Osc mode XT Osc mode LP Osc mode INTOSC mode RC Osc mode XT Osc mode HS Osc mode
Oscillator Frequency(1)
1
TOSC
External CLKIN Period(1)
200 TCY DC ns TCY = 4/FOSC 2* -- -- s LP oscillator, TOSC L/H duty cycle 20* -- -- ns HS oscillator, TOSC L/H duty cycle 100 * -- -- ns XT oscillator, TOSC L/H duty cycle 4 TosR, External CLKIN Rise -- -- 50* ns LP oscillator TosF External CLKIN Fall -- -- 25* ns XT oscillator -- -- 15* ns HS oscillator * These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at `min' values with an external clock applied to OSC1 pin. When an external clock input is used, the `max' cycle time limit is `DC' (no clock) for all devices.
2 3
TCY TosL, TosH
Instruction Cycle Time(1) External CLKIN (OSC1) High External CLKIN Low
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 149
PIC16F785
TABLE 18-2:
Param No. F10 Sym
PRECISION INTERNAL OSCILLATOR PARAMETERS
Characteristic Freq Min Tolerance 1% 2% 5% 7.92 7.84 7.60 Typ 8.00 8.00 8.00 Max 8.08 8.16 8.40 Units Conditions
FOSC Internal Calibrated INTOSC Frequency(1)
F14
-- -- TBD TBD -- -- TBD TBD -- -- TBD TBD * These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1uF and 0.01uF values in parallel are recommended.
TIOSC Oscillator wake-up from ST Sleep start-up time*
MHz VDD = 3.5V, 25C MHz 2.5V VDD 5.5V 0C TA +85C MHz 2.0V VDD 5.5V -40C TA +85C (Ind.) -40C TA +125C (Ext.) s VDD = 2.0V, -40C to +85C s VDD = 3.0V, -40C to +85C s VDD = 5.0V, -40C to +85C
FIGURE 18-4:
CLKOUT AND I/O TIMING
Q4 Q1 Q2 11 22 23 13 14 19 18 12 16 Q3
OSC1 10 CLKOUT
I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 15 New Value
TABLE 18-3:
Param No. 10 11 12 13 14 15 16
CLKOUT AND I/O TIMING REQUIREMENTS
Sym Characteristic Min -- -- -- -- -- TOSC + 200 ns 0 Typ 75 75 35 35 -- -- -- Max 200 200 100 100 20 -- -- Units ns ns ns ns ns ns ns Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckL OSC1 to CLOUT TosH2ckH OSC1 to CLOUT TckR TckF TckL2ioV TioV2ckH TckH2ioI CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
DS41249A-page 150
Preliminary
2004 Microchip Technology Inc.
PIC16F785
TABLE 18-3:
Param No. 17 18 19 20 21 22 23
CLKOUT AND I/O TIMING REQUIREMENTS (CONTINUED)
Sym Characteristic OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Min -- -- 100 0 -- -- 25 TCY Typ 50 -- -- -- 10 10 -- -- Max 150 * 300 -- -- 40 40 -- -- Units ns ns ns ns ns ns ns ns Conditions
TosH2ioV TosH2ioI
TioV2osH Port input valid to OSC1 (I/O in setup time) TioR TioF Tinp Trbp Port output rise time Port output fall time INT pin high or low time PORTA change INT high or low time
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
FIGURE 18-5:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O Pins 32 30
31 34
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 151
PIC16F785
FIGURE 18-6: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset)
36
Reset (due to BOR)
64 ms time-out(1)
Note 1:
64 ms delay only if PWRTE bit in Configuration Word is programmed to `0'.
TABLE 18-4:
Param No. 30 31
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Sym Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Reset Pulse Width Min 2 11 10 10 -- 28* TBD -- Typ -- 18 17 17 1024 TOSC 64 TBD -- Max -- 24 25 30 -- 132* TBD 2.0 Units s ms ms ms -- ms ms s Conditions VDD = 5V, -40C to +85C Extended temperature VDD = 5V, -40C to +85C Extended temperature TOSC = OSC1 period VDD = 5V, -40C to +85C Extended Temperature
TMCL TWDT
32 33* 34
TOST TPWRT TIOZ
35 36
VBOR TBOR
2.025 100*
-- --
2.175 --
V s VDD VBOR (D005)
Legend: TBD = To Be Determined. * These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41249A-page 152
Preliminary
2004 Microchip Technology Inc.
PIC16F785
FIGURE 18-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 41
42
T1CKI 45 47 46 49
TMR0 or TMR1
TABLE 18-5:
Param No. 40* 41* 42*
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 DC Typ -- -- -- -- -- Max -- -- -- -- -- Units Conditions ns ns ns ns ns
Sym Tt0H Tt0L Tt0P
N = prescale value (2, 4, ..., 256)
45*
Tt1H
T1CKI High Time
46*
Tt1L
T1CKI Low Time
47*
Tt1P
T1CKI Input Period
Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous Synchronous
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns
N = prescale value (1, 2, 4, 8)
48
Asynchronous -- -- ns Timer1 oscillator input frequency range -- 200* kHz (oscillator enabled by setting bit T1OSCEN) 49 TCKEZtmr1 Delay from external clock edge to timer 2 TOSC* -- 7 -- increment TOSC* * These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Ft1
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FIGURE 18-8: CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP1 (Capture mode)
50 52
51
CCP1 (Compare or PWM mode)
53 Note: Refer to Figure 18-2 for load conditions.
54
TABLE 18-6:
Param Symbol No. 50* TccL
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Characteristic CCP1 input low time No Prescaler With Prescaler Min 0.5TCY + 20 20 0.5TCY + 20 20 3TCY + 40 N -- -- Typ Max Units -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns N = prescale value (1,4 or 16) Conditions
51*
TccH
CCP1 input high time
No Prescaler With Prescaler
52*
TccP
CCP1 input period
53* 54*
TccR TccF
CCP1 output rise time CCP1 output fall time
25 25
50 45
ns ns
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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TABLE 18-7: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min -- 0 -- +70* -- -- Typ 2 -- -- -- -- -- Max 5 VDD - 1.5 200* -- 20* 40* Units mV V nA dB ns ns Internal Output to pin Comments Comparator Specifications Param No. C01 C02 C03 C04 C05 * Note 1: Symbol VOS VCM ILC CMRR TRT Characteristics Input Offset Voltage Input Common Mode Voltage Input Leakage Current Common Mode Rejection Ratio Response Time(1)
These parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD - 1.5V.
TABLE 18-8:
COMPARATOR VOLTAGE REFERENCE (VREF) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min -- -- -- -- -- -- Typ VDD/24* VDD/32 -- -- 2K* -- Max -- -- 1/4* 1/2* -- 10* Units LSb LSb LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
Comparator Voltage Reference Specifications Param No. CV01 CV02 CV03 CV04 * Note 1: Symbol CVRES Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time
(1)
These parameters are characterized but not tested. Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
TABLE 18-9:
VOLTAGE (VR) REFERENCE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min TBD -- -- -- Typ 1.200 150 200 10 Max TBD TBD -- 100* Units V ppm/C V/V s Comments
VR Voltage Reference Specifications Param No. VR01 VR02 VR03 VR04 Symbol VROUT TCVOUT Characteristics VR voltage output Voltage drift temperature coefficient Voltage drift with respect to VDD regulation Settling Time
VROUT/ VDD
TSTABLE
Legend: TBD = To Be Determined * These parameters are characterized but not tested.
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TABLE 18-10: OPERATIONAL AMPLIFIER (OPA) DC SPECIFICATIONS
OPA DC Characteristics Standard Operating Conditions (unless otherwise stated) VCM = 0V, Vout = VDD/2, VDD = 5V, VSS = 0V, CL = 50pF, RL = 100k Operating temperature -40C TA +125C Characteristics Input Offset Voltage Input current and impedance Input bias current Input offset bias current Common Mode Common mode input range Common mode rejection Open Loop Gain DC Open loop gain DC Open loop gain Output Output voltage swing Min -- -- -- VSS TBD -- -- VSS + 50 Typ 5 2* 1* -- 70 90 60 -- Max -- -- -- VDD - 1.4 -- -- -- VDD - 50 Units mV nA pA V dB dB dB mV VDD = 5V VCM = VDD/2, Freq = DC No load Standard load To VDD/2 (20 k connected to VDD, 20 k + 20 pF to Vss) Comments
Param No. OPA01* OPA02* OPA03* OPA04* OPA05*
Symbol VOS IB IOS VCM CMR
OPA06A* AOL OPA06B* AOL OPA07* Vout
OPA08* OPA10
Isc PSR
Output short circuit current Power Supply Power supply rejection
-- 80
25 --
TBD --
mA dB
Legend: TBD = To Be Determined * These parameters are characterized but not tested.
TABLE 18-11: OPERATIONAL AMPLIFIER (OPA) AC SPECIFICATIONS
OPA AC Characteristics Standard Operating Conditions (unless otherwise stated) VCM = 0V, Vout = VDD/2, VDD = 5V, VSS = 0V, CL = 50pF, RL = 100k Operating temperature -40C TA +125C Characteristics Gain bandwidth product Turn on time Phase margin Slew rate Min -- -- -- 2 Typ 3 10 60 -- Max -- TBD -- -- Units MHz s deg V/s Comments
Param No.
Symbol
OPA11* GBWP OPA12* TON OPA13* M OPA14* SR
Legend: TBD = To Be Determined * These parameters are characterized but not tested.
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TABLE 18-12: PIC16F785 A/D CONVERTER CHARACTERISTICS:
Param No. A01 A02 A03 A04 A05 A06 A07 A10 A20 A20A A25 A30 Sym NR Characteristic Resolution Min -- -- -- -- 2.2* -- -- -- 2.2(4) 2.5 VSS -- Typ -- -- -- -- -- -- -- guaranteed --
(2)
Max 10 bits 1 1 1 5.5* 1 1 -- -- VDD + 0.3 VREF(5) 10
Units bit LSb VREF = 5.0V LSb VREF = 5.0V
Conditions
EABS Total Absolute Error*(1) EIL EDL EFS EGN -- Integral Error Differential Error Full Scale Range Gain Error Monotonicity
LSb No missing codes to 10 bits VREF = 5.0V V LSb VREF = 5.0V LSb VREF = 5.0V -- V Absolute minimum to ensure 10-bit accuracy V k VSS VAIN VREF
EOFF Offset Error
VREF Reference Voltage
VAIN ZAIN
Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF Input Current*(3)
-- --
A50
IREF
10 --
-- --
1000 10
A A
During VAIN acquisition. Based on differential of VHOLD to VAIN. During A/D conversion cycle.
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes Integral, Differential, Offset and Gain Errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: VREF current is from external VREF or VDD pin, whichever is selected as reference input. 4: Only limited when VDD is at or below 2.5V. If VDD is above 2.5V, VREF is allowed to go as low as 1.0V. 5: Analog input voltages are allowed up to VDD, however the conversion accuracy is limited to VSS to VREF.
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FIGURE 18-9: PIC16F785 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY 131 130 A/D CLK A/D DATA ADRES ADIF GO SAMPLE 132 SAMPLING STOPPED 9 8 OLD_DATA 7 6 3 2 1 0 NEW_DATA 1 TCY DONE BSF ADCON0, GO 134 Q4
(TOSC/2)(1)
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 18-13: PIC16F785 A/D CONVERSION REQUIREMENTS
Param No. 130 130 Sym TAD TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time Min 1.6 3.0* 3.0* 2.0* 131 TCNV -- Typ -- -- 6.0 4.0 11 Max -- -- 9.0* 6.0* -- Units s s s s TAD Conditions TOSC-based, VREF 3.0V TOSC-based, VREF full range ADCS<1:0> = 11 (RC mode) At VDD = 2.5V At VDD = 5.0V Set GO bit to new data in A/D result register
132
TACQ
(Note 2) 5*
11.5 --
-- --
s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D Clock Start
--
TOSC/2
--
--
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Table 12-1 for minimum conditions.
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FIGURE 18-10: PIC16F785 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO 134 Q4 130 A/D CLK A/D DATA ADRES ADIF GO SAMPLE 132 SAMPLING STOPPED 9 8 7 6 3 2 1 0 NEW_DATA 1 TCY DONE
(TOSC/2 + TCY)(1)
131
1 TCY
OLD_DATA
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 18-14: PIC16F785 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Param No. 130 Sym TAD Characteristic A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time Min Typ Max Units Conditions ADCS<1:0> = 11 (RC mode) At VDD = 2.5V At VDD = 5.0V
3.0* 2.0* --
6.0 4.0 11
9.0* 6.0* --
s s TAD
131
TCNV
132
TACQ
(Note 2) 5*
11.5 --
-- --
s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D Clock Start
--
TOSC/2 + TCY
--
--
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Table 12-1 for minimum conditions.
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NOTES:
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19.0
19.1
PACKAGING INFORMATION
Package Marking Information
20-Lead PDIP (DIP) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example PIC16F785 -I/P 0415017
20-Lead SOIC XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example PIC16F785 -E/SO 0415017
20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example PIC16F785 -I/SS 0415017
Legend: XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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19.2 Package Details
The following sections give the technical details of the packages.
20-Lead Plastic Dual In-line (P) - 300 mil Body (PDIP)
E1
D
2 n E 1
A
A2
c A1 eB Units Dimension Limits n p B INCHES* NOM 20 .100 .155 .130 B1 p MILLIMETERS NOM 20 2.54 3.56 3.94 2.92 3.30 0.38 7.49 7.87 6.10 6.35 26.04 26.24 3.05 3.30 0.20 0.29 1.40 1.52 0.36 0.46 7.87 9.40 5 10 5 10
L
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .295 .310 .325 Molded Package Width E1 .240 .250 .260 Overall Length D 1.025 1.033 1.040 Tip to Seating Plane L .120 .130 .140 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .055 .060 .065 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-019
4.32 3.68 8.26 6.60 26.42 3.56 0.38 1.65 0.56 10.92 15 15
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20-Lead Plastic Small Outline (SO) - Wide, 300 mil Body (SOIC)
E E1 p
D
2 B n 1
h 45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.093 .088 .004 .394 .291 .496 .010 .016 0 .009 .014 0 0
INCHES* NOM 20 .050 .099 .091 .008 .407 .295 .504 .020 .033 4 .011 .017 12 12
MAX
MIN
.104 .094 .012 .420 .299 .512 .029 .050 8 .013 .020 15 15
MILLIMETERS NOM 20 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 12.60 12.80 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12
MAX
2.64 2.39 0.30 10.67 7.59 13.00 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-094
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20-Lead Plastic Shrink Small Outline (SS) - 209 mil Body, 5.30 mm (SSOP)
E E1 p
D
B n
2 1
c A
A2
L A1
Number of Pins Pitch Overall Height A .079 Molded Package Thickness A2 .065 .073 Standoff A1 .002 Overall Width E .291 .323 Molded Package Width E1 .197 .220 Overall Length D .272 .295 Foot Length L .022 .037 c Lead Thickness .004 .010 Foot Angle 0 8 Lead Width B .009 .015 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150
Drawing No. C04-072
Units Dimension Limits n p
MIN
INCHES NOM 20 .026 .069 .307 .209 .283 .030 4 -
MAX
MIN
MILLIMETERS* NOM 20 0.65 1.65 1.75 0.05 7.40 7.80 5.00 5.30 6.90 7.20 0.55 0.75 0.09 0 4 0.22 -
MAX
2.00 1.85 8.20 5.60 7.50 0.95 0.25 8 0.38
Revised 11/03/03
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APPENDIX A:
Revision A
This is a new data sheet.
DATA SHEET REVISION HISTORY
APPENDIX B:
MIGRATING FROM OTHER PICmicro(R) DEVICES
This discusses some of the issues in migrating from the PIC16F684 PICmicro device to the PIC16F785.
B.1
PIC16F684 to PIC16F785
FEATURE COMPARISON
PIC16F684 20 MHz 2048 128 10-bit 256 2/1 8 Y RA0/1/2/4/5 MCLR PIC16F785 20 MHz 2048 128 10-bit 256 2/1 8 Y RA0/1/2/3/4/5 MCLR 2 ECCP N N Y Y Y 32 kHz 8 MHz Y Y 2 2 Phase N Y Y 32 kHz 8 MHz Y Feature
TABLE B-1:
Max Operating Speed Max Program Memory (Words) SRAM (bytes) A/D Resolution Data EEPROM (bytes) Timers (8/16-bit) Oscillator modes Brown-out Reset Internal Pull-ups Interrupt-on-change Comparator CCP Op Amps PWM Ultra Low-Power Wake-up Extended WDT Software Control Option of WDT/BOR INTOSC Frequencies Clock Switching
RA0/1/2/3/4/5 RA0/1/2/3/4/5
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INDEX
A
A/D ...................................................................................... 77 Acquisition Requirements ........................................... 83 Analog Port Pins ......................................................... 78 Associated registers.................................................... 86 Block Diagram............................................................. 77 Calculating Acquisition Time....................................... 83 Channel Selection....................................................... 78 Configuration and Operation....................................... 78 Configuring.................................................................. 82 Configuring Interrupt ................................................... 82 Conversion Clock........................................................ 78 Effects of a Reset........................................................ 86 Internal Sampling Switch (RSS) Impedance................ 83 Operation During Sleep .............................................. 85 Output Format............................................................. 79 Reference Voltage (VREF)........................................... 78 Source Impedance...................................................... 83 Special Event Trigger.................................................. 86 Specifications............................................ 157, 158, 159 Starting a Conversion ................................................. 79 Using the ECCP Trigger ............................................. 86 Absolute Maximum Ratings .............................................. 139 AC Characteristics Load Conditions ........................................................ 148 ADCON0 Register............................................................... 81 ADCON1 Register............................................................... 81 Analog-to-Digital Converter. See A/D ANSEL Register .................................................................. 80 Assembler MPASM Assembler................................................... 133 RC5 Pin ...................................................................... 46 Resonator Operation .................................................. 25 Timer1 ........................................................................ 49 Timer2 ........................................................................ 54 TMR0/WDT Prescaler ................................................ 47 Two Phase PWM Complementary Output Mode ............................ 96 Simplified Diagram ............................................. 88 Single Phase Example ....................................... 94 VR Reference ............................................................. 72 Watchdog Timer (WDT)............................................ 117 Brown-out Reset (BOR).................................................... 107 Associated registers ................................................. 108 Calibration ................................................................ 107 Specifications ........................................................... 152 Timing and Characteristics ....................................... 152
C
C Compilers MPLAB C17.............................................................. 134 MPLAB C18.............................................................. 134 MPLAB C30.............................................................. 134 Calibration Bits.................................................................. 103 Capture Module. SeeCapture/Compare/PWM (CCP) Capture/Compare/PWM (CCP) .......................................... 55 Associated registers ................................................... 60 Associated registers w/ Capture/Compare/Timer1..... 57 Capture Mode............................................................. 56 CCP1 Pin Configuration ............................................. 56 Compare Mode........................................................... 57 CCP1 Pin Configuration ..................................... 57 Software Interrupt Mode ..................................... 57 Special Event Trigger and A/D Conversions ...... 57 Special Trigger Output........................................ 57 Timer1 Mode Selection....................................... 57 Prescaler .................................................................... 56 PWM Mode................................................................. 58 Duty Cycle .......................................................... 58 Effects of Reset .................................................. 59 Example PWM Frequencies and Resolutions .... 59 Operation in Power Managed Modes ................. 59 Operation with Fail-Safe Clock Monitor .............. 59 Setup for Operation ............................................ 59 Setup for PWM Operation .................................. 59 Specifications ........................................................... 154 Timer Resources ........................................................ 55 CCP. See Capture/Compare/PWM (CCP) CCP1CON Register............................................................ 55 CCPR1H Register............................................................... 55 CCPR1L Register ............................................................... 55 Clock Sources..................................................................... 23 CM1CON0 .......................................................................... 63 CM2CON1 .......................................................................... 66 Code Examples Assigning Prescaler to Timer0.................................... 48 Assigning Prescaler to WDT....................................... 48 Changing Between Capture Prescalers ..................... 56 Data EEPROM Read................................................ 101 Data EEPROM Write ................................................ 101 EEPROM Write Verify .............................................. 101 Indirect Addressing..................................................... 22 Initializing A/D............................................................. 82 Initializing PORTA ...................................................... 33 Initializing PORTB ...................................................... 40
B
Block Diagrams (CCP) Capture Mode Operation ................................. 56 A/D .............................................................................. 77 Analog Input Model ..................................................... 84 CCP PWM................................................................... 58 Clock Source............................................................... 23 Comparator 1 .............................................................. 62 Comparator 2 .............................................................. 64 Compare ..................................................................... 57 CVref........................................................................... 69 Fail-Safe Clock Monitor (FSCM) ................................. 30 In-Circuit Serial Programming Connections.............. 121 Interrupt Logic ........................................................... 114 MCLR Circuit............................................................. 106 On-Chip Reset Circuit ............................................... 105 OPA Module................................................................ 73 PIC16F684.................................................................... 5 RA0 Pin....................................................................... 36 RA1 Pin....................................................................... 36 RA2 Pin....................................................................... 37 RA3 Pin....................................................................... 37 RA4 Pin....................................................................... 38 RA5 Pin....................................................................... 38 RB4 and RB5 Pins. ..................................................... 41 RB6 Pin....................................................................... 41 RB7 Pin....................................................................... 41 RC0 and RC1 Pins...................................................... 41 RC0, RC6 and RC7 Pins ............................................ 44 RC1 Pin....................................................................... 44 RC2 and RC3 Pins...................................................... 45 RC4 Pin....................................................................... 45
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Initializing PORTC....................................................... 43 Interrupt Context Saving ........................................... 116 Code Protection ................................................................ 121 Comparator Module ............................................................ 61 Associated registers.................................................... 72 C1 Output State Versus Input Conditions ................... 61 C2 Output State Versus Input Conditions ................... 64 Comparator Interrupts ................................................. 67 Effects of a RESET ..................................................... 67 Comparator Voltage Reference (CVREF) Specifications ............................................................ 155 Comparators C2OUT as T1 Gate ..................................................... 50 Specifications ............................................................ 155 Compare Module. SeeCapture/Compare/PWM (CCP) CONFIG Register.............................................................. 104 Configuration Bits.............................................................. 103 CPU Features ................................................................... 103
I
ID Locations...................................................................... 121 In-Circuit Debugger........................................................... 122 In-Circuit Serial Programming (ICSP)............................... 121 Indirect Addressing, INDF and FSR registers..................... 22 Instruction Format............................................................. 123 Instruction Set................................................................... 123 ADDLW..................................................................... 125 ADDWF..................................................................... 125 ANDLW..................................................................... 125 ANDWF..................................................................... 125 BCF .......................................................................... 125 BSF........................................................................... 125 BTFSC ...................................................................... 125 BTFSS ...................................................................... 125 CALL......................................................................... 126 CLRF ........................................................................ 126 CLRW ....................................................................... 126 CLRWDT .................................................................. 126 COMF ....................................................................... 126 DECF ........................................................................ 126 DECFSZ ................................................................... 126 GOTO ....................................................................... 127 INCF ......................................................................... 127 INCFSZ..................................................................... 127 IORLW ...................................................................... 127 IORWF...................................................................... 127 MOVF ....................................................................... 127 MOVLW .................................................................... 128 MOVWF .................................................................... 128 NOP .......................................................................... 128 RETFIE ..................................................................... 128 RETLW ..................................................................... 129 RETURN................................................................... 129 RLF ........................................................................... 129 RRF .......................................................................... 130 SLEEP ...................................................................... 130 SUBLW ..................................................................... 130 SUBWF..................................................................... 131 SWAPF ..................................................................... 131 TRIS ......................................................................... 131 XORLW .................................................................... 132 XORWF .................................................................... 132 Summary Table ........................................................ 124 INTCON Register................................................................ 17 Internal Oscillator Block INTOSC Specifications ................................................... 150 Internal Sampling Switch (RSS) Impedance........................ 83 Interrupts........................................................................... 113 (CCP) Compare .......................................................... 57 A/D.............................................................................. 82 Associated registers ................................................. 115 Comparator................................................................. 67 Context Saving ......................................................... 116 Data EEPROM Memory Write .................................. 100 Interrupt-on-change .................................................... 35 Oscillator Fail (OSF) ................................................... 30 PORTA Interrupt-on-change..................................... 114 RA2/INT .................................................................... 114 TMR0 ........................................................................ 114 TMR1 .......................................................................... 50 TMR2 to PR2 Match ............................................. 53, 54 INTOSC Specifications ..................................................... 150 IOCA (interrupt-on-change) ................................................ 35 IOCA Register..................................................................... 35
D
Data EEPROM Memory Associated registers.................................................. 102 Code Protection .................................................. 99, 102 Data Memory......................................................................... 9 DC Characteristics Extended and Industrial ............................................ 146 Industrial and Extended ............................................ 141 Demonstration Boards PICDEM 1 ................................................................. 136 PICDEM 17 ............................................................... 137 PICDEM 18R ............................................................ 137 PICDEM 2 Plus ......................................................... 136 PICDEM 3 ................................................................. 136 PICDEM 4 ................................................................. 136 PICDEM LIN ............................................................. 137 PICDEM USB............................................................ 137 PICDEM.net Internet/Ethernet .................................. 136 Development Support ....................................................... 133 Device Overview ................................................................... 5
E
EEADR Register ................................................................. 99 EECON1 Register ............................................................. 100 EECON2 Register ............................................................. 100 EEDAT Register.................................................................. 99 EEPROM Data Memory Avoiding Spurious Write............................................ 101 Reading..................................................................... 101 Write Verify ............................................................... 101 Writing ....................................................................... 101 Electrical Specifications .................................................... 139 Errata .................................................................................... 3 Evaluation and Programming Tools .................................. 137
F
Fail-Safe Clock Monitor....................................................... 30 Fail-Safe Condition Clearing ....................................... 31 Reset and Wake-up from Sleep .................................. 31 Firmware Instructions........................................................ 123 Fuses. See Configuration Bits
G
General Purpose Register File.............................................. 9
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L
Load Conditions ................................................................ 148
M
MCLR ................................................................................ 106 Internal ...................................................................... 106 Memory Organization............................................................ 9 Data .............................................................................. 9 Data EEPROM Memory.............................................. 99 Program ........................................................................ 9 Migrating from other PICmicro Devices ............................ 165 MPLAB ASM30 Assembler, Linker, Librarian ................... 134 MPLAB ICD 2 In-Circuit Debugger ................................... 135 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ......................................................................... 135 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator ......................................................................... 135 MPLAB Integrated Development Environment Software .. 133 MPLAB PM3 Device Programmer .................................... 135 MPLINK Object Linker/MPLIB Object Librarian ................ 134
O
OPA Module Associated Registers .................................................. 75 OPA1CON .......................................................................... 74 OPA2CON .......................................................................... 74 OPCODE Field Descriptions ............................................. 123 Operational Amplifier (OPA) Module................................... 73 Operational Amplifier (Opa) Module ................................... 73 OPTION_REG Register ...................................................... 16 OSCCON Register .............................................................. 32 Oscillator Associated registers.................................................... 32 Oscillator Specifications .................................................... 149 Oscillator Start-up Timer (OST) Specifications............................................................ 152 Oscillator Switching Fail-Safe Clock Monitor............................................... 30 Two-Speed Clock Start-up.......................................... 29
P
Packaging ......................................................................... 161 Marking ..................................................................... 161 Packaging Details ..................................................... 162 PCL and PCLATH ............................................................... 21 Stack ........................................................................... 21 PCON Register ................................................................. 108 PICkit 1 Flash Starter Kit................................................... 137 PICSTART Plus Development Programmer ..................... 136 PIE1 Register ...................................................................... 18 Pin Diagram .......................................................................... 2 Pinout Descriptions PIC16F684.................................................................... 6 PIR1 Register...................................................................... 19 PORC RC2............................................................................. 45 PORTA................................................................................ 33 Additional Pin Functions ............................................. 34 Interrupt-on-change ............................................ 35 Weak Pull-up ...................................................... 34 Associated registers.................................................... 39 Pin Descriptions and Diagrams................................... 36 RA0 ............................................................................. 36 RA1 ............................................................................. 36 RA2 ............................................................................. 37 RA3 ............................................................................. 37
RA4............................................................................. 38 RA5............................................................................. 38 Specifications ........................................................... 150 PORTB ............................................................................... 40 Associated registers ................................................... 42 Pin Descriptions and Diagrams .................................. 41 RB4............................................................................. 41 RB5............................................................................. 41 RB6............................................................................. 41 RB7............................................................................. 41 PORTC ............................................................................... 43 Associated registers ............................................. 32, 46 Pin Descriptions and Diagrams .................................. 44 RC0 ............................................................................ 44 RC1 ............................................................................ 44 RC3 ............................................................................ 45 RC4 ............................................................................ 45 RC5 ............................................................................ 46 RC6 ............................................................................ 44 RC7 ............................................................................ 44 Specifications ........................................................... 150 Power-Down Mode (Sleep)............................................... 119 Power-up Timer (PWRT) .................................................. 106 Specifications ........................................................... 152 Power-up Timing Delays................................................... 108 Precision Internal Oscillator Parameters .......................... 150 Prescaler Shared WDT/Timer0................................................... 48 Switching Prescaler Assignment ................................ 48 PRO MATE II Universal Device Programmer ................... 135 Product Identification ........................................................ 176 Program Memory .................................................................. 9 Map and Stack.............................................................. 9 Programming, Device Instructions.................................... 123 PWM. See Two Phase PWM PWMCLK Register.............................................................. 90 PWMCON0 Register........................................................... 89 PWMCON1 Register........................................................... 95 PWMPH1 Register.............................................................. 91 PWMPH2 Register.............................................................. 92
R
Read-Modify-Write Operations ......................................... 123 REFCON (VR control) ........................................................ 71 Register IOCA (interrupt-on-change) ........................................ 35 WPUA (Weak pullup).................................................. 34 Registers ADCON0 (A/D Control 0)............................................ 81 ADCON1 (A/D Control 1)............................................ 81 ANSEL (Analog Select) .............................................. 80 CCP1CON (CCP Operation) ...................................... 55 CCPR1H..................................................................... 55 CCPR1L ..................................................................... 55 CM1CON0 (C1 Control) ............................................. 63 CM1CON0 (C2 Control) CM2CON0 .......................................................... 65 CM2CON1 (C2 control) .............................................. 66 CONFIG (Configuration Word) ................................. 104 Data Memory Map ...................................................... 10 EEADR (EEPROM Address) ...................................... 99 EECON1 (EEPROM Control 1) ................................ 100 EECON2 (EEPROM Control 2) ................................ 100 EEDAT (EEPROM Data) ............................................ 99 INTCON (Interrupt Control) ........................................ 17 IOCA (Interrupt-on-change PORTA) .......................... 35
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PIC16F785
OPAMP Control Register (OPACON) ......................... 74 OPTION_REG (Option) .............................................. 16 OSCCON (Oscillator Control) ..................................... 32 PCON (Power Control) ............................................. 108 PIE1 (Peripheral Interrupt Enable 1) ........................... 18 PIR1 (Peripheral Interrupt Register 1) ........................ 19 PORTA........................................................................ 33 PORTB........................................................................ 40 PORTC ....................................................................... 43 PWMCLK (PWM clock control) ................................... 90 PWMCON0 (PWM control 0) ...................................... 89 PWMCON1 (PWM control 1) ...................................... 95 PWMPH1 (PWM Phase 1 control) .............................. 91 PWMPH2 (PWM Phase 2 control) .............................. 92 REFCON (VR control)................................................. 71 Reset Values (special registers) ............................... 112 Special Function registers............................................. 9 Special Register Summary ....................... 11, 12, 13, 14 Status .......................................................................... 15 T1CON (Timer1 Control)............................................. 51 T2CON (Timer2 Control)............................................. 53 TRISA (Tristate PORTA)............................................. 34 TRISB (Tristate PORTB)............................................. 40 TRISC (Tristate PORTC) ............................................ 43 WDTCON (Watchdog Timer Control)........................ 118 WPUA (Weak Pull-up PORTA) ................................... 34 Resets ............................................................................... 105 Power-On Reset ....................................................... 106 Revision History ................................................................ 165 RRF Instruction ................................................................. 130 Timer2................................................................................. 53 Associated registers ................................................... 54 Operation .................................................................... 53 Postscaler ................................................................... 53 PR2 Register .............................................................. 53 Prescaler .................................................................... 53 TMR2 Register............................................................ 53 TMR2 to PR2 Match Interrupt............................... 53, 54 Timing Diagrams A/D Conversion......................................................... 158 A/D Conversion (Sleep Mode) .................................. 159 Brown-out Reset (BOR)............................................ 152 Brown-out Reset Situations ...................................... 107 Capture/Compare/PWM (CCP) ................................ 154 CLKOUT and I/O ...................................................... 150 External Clock........................................................... 148 Fail-Safe Clock Monitor (FSCM)................................. 31 INT Pin Interrupt ....................................................... 115 Reset, WDT, OST and Power-up Timer ................... 151 Time-out Sequence Case 1 .............................................................. 109 Case 2 .............................................................. 109 Case 3 .............................................................. 109 Timer0 and Timer1 External Clock ........................... 153 Timer1 Incrementing Edge ......................................... 50 Two Phase PWM Auto-Shutdown ................................................... 93 Complementary Output ...................................... 96 Startup ................................................................ 93 System Timing.................................................... 92 Two Speed Start-up.................................................... 30 Wake-up from Interrupt............................................. 120 Timing Parameter Symbology .......................................... 148 TRIS Instruction ................................................................ 131 TRISA Register................................................................... 34 TRISB Register................................................................... 40 TRISC Register................................................................... 43 Two Phase PWM ................................................................ 87 Activating .................................................................... 87 Active output level ...................................................... 88 Associated registers ................................................... 97 Auto shutdown ............................................................ 88 Clock control (PWMCLK)............................................ 90 Control Register 0 (PWMCON0)................................. 89 Control Register 1 (PWMCON1)................................. 95 Master/Slave Operation .............................................. 87 Output Blanking .......................................................... 87 Phase 1 control (PWMPH1)........................................ 91 Phase 2 control (PWMPH1)........................................ 92 PWM Duty Cycle......................................................... 87 PWM Frequency ......................................................... 87 PWM Period................................................................ 87 PWM Phase................................................................ 87 PWM Phase resolution ............................................... 87 Shutdown.................................................................... 88 Two-Speed Clock Start-up Mode........................................ 29
S
SLEEP Instruction ............................................................. 130 Software Simulator (MPLAB SIM)..................................... 134 Software Simulator (MPLAB SIM30)................................. 134 Special Event Trigger.......................................................... 86 Special Function registers..................................................... 9 Status Register.................................................................... 15 SUBLW Instruction............................................................ 130 SUBWF Instruction............................................................ 131 SWAPF Instruction............................................................ 131
T
Time-out Sequence........................................................... 108 Timer0 ................................................................................. 47 Associated registers.................................................... 48 External Clock ............................................................. 48 Interrupt....................................................................... 47 Operation .................................................................... 47 Prescaler ..................................................................... 48 Specifications ............................................................ 153 Timer1 ................................................................................. 49 Associated registers.................................................... 52 Asynchronous Counter Mode ..................................... 52 Reading and Writing ........................................... 52 Interrupt....................................................................... 50 Modes of Operations................................................... 50 Operation During Sleep .............................................. 52 Oscillator ..................................................................... 52 Prescaler ..................................................................... 50 Specifications ............................................................ 153 Timer1 Gate Inverting Gate ..................................................... 50 Selecting Source................................................. 50 TMR1H Register ......................................................... 49 TMR1L Register .......................................................... 49
V
Voltage References ............................................................ 69 Associated registers ................................................... 72 Configuring CVref ....................................................... 69 CVref (Comparator Reference)................................... 69 CVref Accuracy........................................................... 69 Fixed VR reference..................................................... 71 VR Stabilization .......................................................... 72 VREF. SEE A/D Reference Voltage
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2004 Microchip Technology Inc.
PIC16F785
W
Wake-up Using Interrupts ................................................. 119 Watchdog Timer (WDT) .................................................... 117 Associated registers.................................................. 118 Clock Source............................................................. 117 Modes ....................................................................... 117 Period........................................................................ 117 Specifications............................................................ 152 WDTCON Register ........................................................... 118 WPUA (weak pullup) ........................................................... 34 WPUA Register ................................................................... 34 WWW, On-Line Support ....................................................... 3
X
XORLW Instruction ........................................................... 132 XORWF Instruction ........................................................... 132
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NOTES:
DS41249A-page 172
Preliminary
2004 Microchip Technology Inc.
PIC16F785
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site.
SYSTEMS INFORMATION AND UPGRADE HOT LINE
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 042003
Connecting to the Microchip Internet Web Site
The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
DS41249A-page 173
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2004 Microchip Technology Inc.
PIC16F785
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F785 Questions: 1. What are the best features of this document? Y N Literature Number: DS41249A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 174
PIC16F785
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device 16F: Standard VDD range 16FT: (Tape and Reel) PIC16F785 - E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 PIC16F785 - I/SO = Industrial Temp., SOIC package, 20 MHz
Temperature Range
I E
= =
-40C to +85C -40C to +125C
Package
P SO SS
= = =
PDIP SOIC (Gull wing, 300 mil body) SSOP(5.3 mm)
Pattern
3-Digit Pattern Code for QTP (blank otherwise)
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 175
WORLDWIDE SALES AND SERVICE
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08/16/04
DS41249A-page 176
Preliminary
2004 Microchip Technology Inc.

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